参数资料
| 型号： | ISL9112IRT7Z-T7A |
| 厂商： | Intersil |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST SYNC 5V 12TDFN |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 1.8 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 2.5MHz |
| 电流 - 输出： | 1.2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 12-TDFN-EP（3x3） |
| 其它名称： | ISL9112IRT7Z-T7ADKR |
ISL9110, ISL9112
Analog Specifications V VIN = V PVIN = V EN = 3.6V, V OUT = 3.3V, L1 = 2.2μH, C1 = C2 = 10μF, T A = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8) (Note 9) (Note 8)
UNITS
LOGIC INPUTS
I LEAK
Input Leakage
0.05
1
μA
V IH
V IL
Input HIGH Voltage
Input LOW Voltage
1.4
0.4
V
V
I 2 C Interface Timing Specification
For SCL, and SDA pins, unless otherwise noted.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
(Note 9) (Note 8) UNITS
C pin
f SCL
t sp
Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA
and SCL Inputs
(Note 11)
(Note 11)
Any pulse narrower than the max spec is
suppressed (Note 11)
15
400
50
pF
kHz
ns
t AA
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing V IL , until SDA exits the
V IL to V IH window (Note 11)
900
ns
t BUF
t LOW
t HIGH
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
t HD:STO
t DH
Time the Bus Must be Free Before the
Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Set-up Time
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for Read, or
Volatile Only Write
Output Data Hold Time
SDA crossing V IH during a STOP condition, to SDA
crossing V IH during the following START
condition (Note 11)
Measured at the V IL crossings (Note 11)
Measured at the V IH crossings (Note 11)
SCL rising edge to SDA falling edge; both
crossing V IH (Note 11)
From SDA falling edge crossing V IL to SCL falling
edge crossing V IH (Note 11)
From SDA exiting the V IL to V IH window, to SCL
rising edge crossing V IL (Note 11)
From SCL rising edge crossing V IH to SDA
entering the V IL to V IH window (Note 11)
From SCL rising edge crossing V IH , to SDA rising
edge crossing V IL (Note 11)
From SDA rising edge to SCL falling edge; both
crossing V IH (Note 11)
From SCL falling edge crossing V IL , until SDA
enters the V IL to V IH window (Note 11)
1300
1300
600
600
600
100
0
600
1300
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t R
t F
Cb
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
From V IL to V IH (Note 11)
From V IH to V IL (Note 11)
Total on-chip and off-chip (Note 11)
20 + 0.1 x Cb
20 + 0.1 x Cb
10
250
250
400
ns
ns
pF
Rpu
SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by t R and t F
For Cb = 400pF, max is about 2k Ω ~2.5k Ω
1
k Ω
For Cb = 40pF, max is about 15k Ω ~20k Ω
(Note 11)
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Typical values are for T A = +25°C and V IN = 3.6V.
10. Quiescent current measurements are taken when the output is not switching.
11. ISL9112 only. Limits established by characterization and are not production tested.
7
FN7649.2
July 13, 2012
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| ISL9112IRTNZ-T7A | 功能描述:IC REG BUCK BST SYNC 3.3V 12TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:1 系列:EZBuck™ 类型:降压（降压） 输出类型:可调式 输出数:1 输出电压:0.8 V ~ 22.1 V 输入电压:3 V ~ 26 V PWM 型:电流模式 频率 - 开关:1.5MHz 电流 - 输出:1.8A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 包装:剪切带 (CT) 供应商设备封装:8-DFN（2x2） 其它名称:785-1276-1 |
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