参数资料
型号: ISL9112IRT7Z-T7A
厂商: Intersil
文件页数: 14/20页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC 5V 12TDFN
标准包装: 1
类型: 降压(降压),升压(升压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 1.8 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 2.5MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 12-WFDFN 裸露焊盘
包装: 标准包装
供应商设备封装: 12-TDFN-EP(3x3)
其它名称: ISL9112IRT7Z-T7ADKR
ISL9110, ISL9112
TABLE 1. REGISTER ADDRESS 0x00: VOLTAGE CONTROL
TABLE 2. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE (Continued)
BIT NAME TYPE RESET DESCRIPTION
4:0 DCDOUT R/W 00000 V OUT programming. See Table 2.
5 ULTRA R/W 0 Ultrasonic mode select. Not applicable in
forced PWM mode:
0: Ultrasonic feature disabled
1: Ultrasonic feature enabled
DCDOUT[4:0]
0b10010
0b10011
0b10100
OUTPUT VOLTAGE
(V)
3.7
3.8
3.9
6 Reserved R/W
0
0b10101
4.0
7
I2CEN
R/W
0
I 2 C programming enable bit:
0: Device ignores I 2 C command, and uses
0b10110
0b10111
4.1
4.2
last programmed DCDOUT and ULTRA
settings; or if no I 2 C communication has
occurred since POR, the factory
programmed default DCDOUT and ULTRA
settings are used.
1: Device uses the I 2 C programmed
DCDOUT and ULTRA settings.
Bits DCDOUT[4:0] set the output voltage, as shown in Equation 1
and Table 2. The ISL9112 output voltage range is 1.9V to 5.0V.
0b11000
0b11001
0b11010
0b11011
0b11100
0b11101
4.3
4.4
4.5
4.6
4.7
4.8
V OUT = 1.9V + ( n ? 0.1V ) , where n = 0 to 31
(EQ. 1)
0b11110
0b11111
4.9
5.0
A safety mechanism is provided to prevent unintentional changes to
the output voltage by errant host software. The MSB of the control
register (I2CEN bit, see Table 1) must be set to ‘1’ in order for the
ISL9112 to recognize the I 2 C command as valid. If a value of ‘0’ is
written to this bit, the I 2 C command is ignored, and output voltage
and operating mode will revert to the factory programmed default
(3.3V for ISL9112IRTNZ; 5V for ISL9112IRT7Z).
TABLE 2. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE
BIT
2:0
TABLE 3. REGISTER ADDRESS 0x01: SLEW RATE CONTROL
NAME TYPE RESET DESCRIPTION
SLEWRATE R/W 000 Slew rate control (typ),
expressed as μs per LSB
change in DCDOUT value:
0b000 = 0μs/ Δ LSB
0b001 = 1.5μs/ Δ LSB
DCDOUT[4:0]
0b00000
0b00001
OUTPUT VOLTAGE
(V)
1.9
2.0
0b010 = 3.1μs/ Δ LSB
0b011 = 6.3μs/ Δ LSB
0b100 = 12.5μs/ Δ LSB
0b101 = 25μs/ Δ LSB
0b110 = 50μs/ Δ LSB
0b111 = 100μ / Δ LSB
0b00010
2.1
7:3
Reserved
R/W
00000
0b00011
0b00100
0b00101
0b00110
0b00111
0b01000
0b01001
0b01010
0b01011
0b01100
0b01101
0b01110
0b01111
0b10000
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
I 2 C Serial Interface (ISL9112)
The ISL9112 supports a bi-directional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL9112 operates as a slave device in all
applications.
All communication over the I 2 C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 28). Upon
power-up of the ISL9112, the SDA pin is in the input mode.
0b10001
14
3.6
FN7649.2
July 13, 2012
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