参数资料
| 型号： | ISL9112IRT7Z-T7A |
| 厂商： | Intersil |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST SYNC 5V 12TDFN |
| 标准包装： | 1 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 1.8 V ~ 5.5 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 2.5MHz |
| 电流 - 输出： | 1.2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 12-TDFN-EP（3x3） |
| 其它名称： | ISL9112IRT7Z-T7ADKR |
ISL9110, ISL9112
All I 2 C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL9112 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 28). A START condition is ignored
during the power-up sequence and when EN input is low.
All I 2 C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 28). A STOP condition at the end of a write
operation initiates the reconfiguration of the ISL9112’s voltage
feedback loop as necessary to provide the programmed output
voltage.
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see
Figure 29).
The ISL9112 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of a Register Address Byte. The ISL9112
also responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 0b0011100 as the seven
MSBs, corresponding to the ISL9112 I 2 C Slave Address. The LSB
of the Identification byte is the Read/Write bit. Its value is “1” for
a Read operation, and “0” for a Write operations (see Table 4).
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte (containing the Slave Address with the R/W
bit set to 0), a valid Register Address Byte, a Data Byte, and a
STOP condition. After each of the three bytes, the ISL9112
responds with an ACK. The master will then send a STOP to
complete the command.
STOP conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and its
associated ACK signal. If a STOP condition is issued in the middle
of a data byte, or before 1 full data byte + ACK is sent, then the
ISL9112 will ignore the command, and not change output
voltage or other settings.
Read Operation
A Read operation is shown in Figure 31. It consists of 4 bytes. The
host generates a START condition, then transmits an Identification
byte (containing the Slave Address with the R/W bit set to 0). The
ISL9112 responds with an ACK. The host then transmits the
Register Address byte, and the ISL9112 responds with another ACK.
The host then generates a Repeat START condition, or a STOP
condition followed by a START condition. The host then transmits
an Identification byte (containing the Slave Address with the R/W
bit set to 1). The ISL9112 responds with an ACK, indicating it is
ready to begin providing the requested data.
The ISL9112 then transmits the data byte by asserting control of
the SDA pin while the host generates clock pulses on the SCL pin.
When transmission of the data byte is complete, the host
0
(MSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
0 1 1 1 0
0
R/W
(LSB)
generates a NACK condition followed by a STOP condition. This
completes the I 2 C Read operation.
The ISL9112 register map supports only one register, at register
address 0x00. Attempts to read other register addresses are not
supported, and should not be attempted. Similarly, I 2 C block
reads and writes are not supported by the ISL9112. The ISL9112
has only one register to read or write, therefore block reads and
writes are not necessary.
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 28. VALID DATA CHANGES, START AND STOP CONDITIONS
15
FN7649.2
July 13, 2012
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相关代理商/技术参数 |
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|---|---|
| ISL9112IRTNEVAL1Z | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:1.2A High Efficiency Buck-Boost Regulators |
| ISL9112IRTNZ | 制造商:Intersil Corporation 功能描述: 制造商:Intersil Corporation 功能描述:1.2A SINGLE INDUCTOR BUCK-BOOST, 3.3V, 12LD 3X3 EP TDFN - Trays |
| ISL9112IRTNZ-EVAL1Z | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:1.2A High Efficiency Buck-Boost Regulators Output Current: Up to 1.2A |
| ISL9112IRTNZ-T | 制造商:Intersil Corporation 功能描述:1.2A SINGLE INDUCTOR BUCK-BOOST, 3.3V, 12LD 3X3 EP TDFN - Tape and Reel |
| ISL9112IRTNZ-T7A | 功能描述:IC REG BUCK BST SYNC 3.3V 12TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:1 系列:EZBuck™ 类型:降压（降压） 输出类型:可调式 输出数:1 输出电压:0.8 V ~ 22.1 V 输入电压:3 V ~ 26 V PWM 型:电流模式 频率 - 开关:1.5MHz 电流 - 输出:1.8A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WFDFN 裸露焊盘 包装:剪切带 (CT) 供应商设备封装:8-DFN（2x2） 其它名称:785-1276-1 |
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