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参数资料
| 型号： | ISL95210HRZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10A 32QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.16 V |
| 输入电压： | 2.97 V ~ 5.5 V |
| PWM 型： | R4 |
| 频率 - 开关： | 400kHz ~ 800kHz |
| 电流 - 输出： | 10A |
| 同步整流器： | 是 |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 32-QFN（4x6） |
| 其它名称： | ISL95210HRZ-T7ADKR |
ISL95210
2.5mV/μs. Table 2 shows the output voltage as dictated by MPCT
and MSEL.
TABLE 2. OUTPUT VOLTAGE MARGINING CONTROL
flexible and easy to design with minimal components. A
complete point of load regulator can be designed with the
ISL95210 using only 4 external components.
MSEL
0
0
0
MPCT
0
FLOAT
1
RESULT
NO MARGINING
NO MARGINING
NO MARGINING
Figure 26 shows the basic error-amplifier configuration for the
R4? controller. A hysteretic comparator monitors the synthetic
current signal against the error voltage and corresponding
window voltage to determine the PWM switching events.
HYSTERETIC WINDOW
FLOAT
0
MARGIN DOWN DAC - 15%
+
VOLTAGE
SYNTHETIC
VW
CURRENT
FLOAT
FLOAT
1
FLOAT
1
0
MARGIN DOWN DAC - 10%
MARGIN DOWN DAC - 20%
MARGIN UP DAC + 15%
VOUT
VDAC
ERROR-
AMPLIFIER
-
COMP VOLTAGE
PWM
1
FLOAT
MARGIN UP DAC + 10%
FIGURE 26. BASIC R4 ? PWM SIGNAL GENERATION
1 1 MARGIN UP DAC + 20%
NOTE: 1 = Input High, 0 = Input Low, FLOAT = Input unconnected or high-Z
(see “Electrical Specifications” table for details).
Each of the margin targets represents the DAC code nearest to
the desired value. Table 3 shows the actual targets for each
margin setting (see Table 4 on page 17 for the full output truth
table).
TABLE 3. OUTPUT VOLTAGE MARGIN TARGETS
STABILITY
The R4? balanced architecture creates a control loop that does
not require compensation for an extremely wide range of output
filters (LOUT, COUT). However, there are corners of operation that
will destabilize the loop and result in oscillatory behavior in VOUT.
The filters that push the control loop toward instability are ones
that add a considerable amount of phase delay to the output
voltage. In general, phase delay increases as output capacitance
decreases in conjunction with reduced output capacitor
D ? D
VOUT
0.600
0.750
0.900
1.000
1.050
1.100
1.200
1.500
1.800
-20%
0.481
0.600
0.719
0.800
0.838
0.881
0.963
1.200
1.438
-15%
0.513
0.638
0.763
0.850
0.894
0.938
1.019
1.275
1.531
-10%
0.538
0.675
0.813
0.900
0.944
0.988
1.081
1.350
1.619
+10%
0.663
0.825
0.988
1.100
1.156
1.213
1.319
1.650
1.981
+15%
0.688
0.863
1.038
1.150
1.206
1.263
1.381
1.7250
2.069
+20%
0.719
0.900
1.081
1.200
1.263
1.325
1.438
1.800
2.163
equivalent series resistance (ESR). For this reason, output filters
that are all-ceramic based have the most difficulty achieving
stable regulation.
The first indication that the ISL95210 is nearing instability is
when its step load response begins to have ring-back. Ring-back
occurs when the PWM on pulse in response to a sharp increase
in output load is so long as to cause the output voltage to
overshoot the regulation point before fully recovering. Equation 4
approximates the boundary condition between normal recovery
and ring-back as a function of operating parameters
[ COUT ? ESR + K ? LOUT ? COUT ] > ISTEP ? ---------------------------- (EQ. 4)
FSW ? Δ IL
where:
Both the DAC and margining features can be used “on the fly”,
meaning the voltage can be changed during normal operation.
Regulation
R4 ? MODULATOR
The R4 modulator is an advanced current-mode hysteretic
control scheme that generates a synthetic current signal on chip
instead of measuring real current. This has the benefit of
-
-
-
-
-
-
-
-
COUT = Total output capacitance in Farads
LOUT = Output inductance in Henries
D = Steady-state duty cycle (VOUT / VIN)
ESR = Output capacitor equivalent series resistance
ISTEP = Expected load step (worst case is preferred)
Δ IL = Inductor ripple current
FSW = Switching frequency
K = Modulator factor:
producing a cleaner and lower jitter system versus conventional
current-mode hysteretic architectures.
R4? also employs a highly balanced architecture that greatly
reduces the need for high DC loop gain traditionally required for
output voltage regulation accuracy. This allows the R4?
modulator to accurately regulate without the need for an
integrator in the feedback loop. Another benefit of the balanced
system is that it does not require compensation for stability over
a wide range of designs. The result is a power solution that is
12
- 3700 for 400kHz FSW
- 4933 for 533kHz FSW
- 7400 for 800kHz FSW
As good design practices dictate, a system should be designed
safely away from this boundary to cover any tolerance shifts that
may occur. For example, if the output capacitor in Figure 1 is
replaced with low-ESR ceramics and reduced until the inequality
FN6938.4
December 15, 2011
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