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参数资料
| 型号： | ISL95210HRZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10A 32QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.16 V |
| 输入电压： | 2.97 V ~ 5.5 V |
| PWM 型： | R4 |
| 频率 - 开关： | 400kHz ~ 800kHz |
| 电流 - 输出： | 10A |
| 同步整流器： | 是 |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 32-QFN（4x6） |
| 其它名称： | ISL95210HRZ-T7ADKR |
ISL95210
in Equation 4 is not met, transient ring-back performance similar
to what is shown in Figure 27 will occur.
This result shows a clean, stable solution when the inequality is
satisfied. It should be noted that when the capacitance in this
example is decremented between 120μF and 76μF, the severity
and frequency of ring-back increases. It can occur prior to
violating Equation 4. This is due to the non-idealities that exist in
real systems and some simplifications in the derivation process.
Care should be taken to design away from the boundary
condition. The above example became fully stable (zero
VOUT (AC)
2μs/DIV
20mV/DIV
VIN = 5V
VOUT = 1.2V
ISTEP = 0-6A
ring-back) when the inequality’s percentage difference was
~35%.
TRANSIENT RESPONSE
As with all current-mode hysteretic style controllers, the
ISL95210 will increase and decrease switching frequency in
response to load transient events. This oversampling quickens
the converters response and minimizes output voltage deviation.
The change in frequency is achieved by the movement on the
COMP voltage seen in Figure 26. When the load current changes
up or down, there is an proportional movement on COMP. The
movement on COMP naturally changes the hysteretic window
size for both PWM edges. Upward swings in COMP (due to
FSW = 800kHz
FIGURE 27. ISL95210 LOAD TRANSIENT RESPONSE WITH
RING-BACK CONDITIONS FROM EXCESSIVE VOUT
PHASE DELAY
In this example, the total output capacitance was 76μF with an
ESR of approximately 1m Ω . When the values are put into
Equation 4, the inequality is not met:
x 3.12·10 -7 > 3.25·10 -7
If additional ceramics are added to increase COUT to 120μF with
an ESR of approximately 0.67m Ω , the ring-back condition is
eliminated, providing the transient results seen in Figure 28.
increasing load current) make the effective hysteretic window
larger during PWM on times and smaller during PWM off times.
The result is increased switching frequency.
Conversely, downward swings in COMP (due to decreasing load
current) make the effective hysteretic window smaller during
PWM on times and larger during PWM off times. Switching
frequency is reduced in this scenario. Figure 29 illustrates the
idealized effect on switching frequency from movements in
COMP in response to load transient events.
IOUT
SYNTHETIC
HYSTERETIC WINDOW
VOLTAGE
COMP VOLTAGE
CURRENT
VOUT (AC)
2μs/DIV
20mV/DIV
VIN = 5V
VOUT = 1.2V
ISTEP = 0-6A
FSW = 800kHz
PWM
VOUT
BOTH PWM EDGES ARE MODULATED DURING LOAD TRANSIENT
FIGURE 29. IDEALIZED EFFECT OF LOAD TRANSIENTS ON
SWITCHING FREQUENCY
Unlike more traditional current-mode hysteretic architectures,
R4? does not require an error-integrating capacitor in the
feedback loop. This removes significant delay in the control loop
FIGURE 28. ISL95210 LOAD TRANSIENT RESPONSE WITHOUT
RING-BACK CONDITIONS
When the new values are evaluated in Equation 4, the following
results are observed:
4.53·10 -7 > 3.25·10 -7
13
and produces extremely fast transient response to changes in
load current.
The speed of response allows system designers to use less
output capacitance and save on board area and cost.
Figure 30 depicts a comparison of the R4? modulator vs. various
classic architectures in response to a load step-up transient. The
FN6938.4
December 15, 2011
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