参数资料
型号: ISL95872HRUZ-T
厂商: Intersil
文件页数: 13/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16UTQFN
标准包装: 3,000
PWM 型: R4
输出数: 1
频率 - 最大: 300kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 16-UFQFN
包装: 带卷 (TR)
ISL95872
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required V P-P is achieved. The
inductance of the capacitor can significantly impact the output
voltage ripple and cause a brief voltage spike if the load transient
has an extremely high slew rate. Low inductance capacitors should
be considered. A capacitor dissipates heat as a function of RMS
current and frequency. Be sure that I P-P is shared by a sufficient
quantity of paralleled capacitors so that they operate below the
maximum rated RMS current at F SW . Take into account that the
rated value of a capacitor can fade as much as 50% as the DC
voltage across it increases.
Selecting the Input Capacitor
In addition to the bulk capacitors, some low ESL ceramic
capacitors are recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
Selecting the Bootstrap Capacitor
The integrated driver features an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
capacitor voltage rating is selected to be at least 10V. Although the
theoretical maximum voltage of the capacitor is PVCC-V DIODE
(voltage drop across the boot diode), large excursions below
ground by the phase node requires at least a 10V rating for the
bootstrap capacitor. The bootstrap capacitor can be chosen from
Equation 16:
C BOOT ≥ ------------------------
0.6
0.5
0.4
x=0
Where:
Q GATE
Δ V BOOT
(EQ. 16)
0.3
0.2
0.1
x=1
x = 0.5
- Q GATE is the amount of gate charge required to fully charge
the gate of the upper MOSFET
- Δ V BOOT is the maximum decay across the BOOT capacitor
As an example, suppose the high-side MOSFET has a total gate
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of 200mV. The
calculated bootstrap capacitance is 0.125μF; for a comfortable
margin, select a capacitor that is double the calculated
DUTY CYCLE
FIGURE 15. NORMALIZED INPUT RMS CURRENT FOR EFF = 1
The important parameters for the bulk input capacitors are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 15 is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle that is
adjusted for converter efficiency. The ripple current calculation is
written as Equation 14:
capacitance. In this example, 0.22μF will suffice. Use a low
temperature-coefficient ceramic capacitor.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function of
the switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for a
desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level will
push the IC beyond the maximum recommended operating
junction temperature of +125°C. When designing the
application, it is recommended that the following calculation be
performed to ensure safe operation at the desired frequency for
the selected MOSFETs. The power dissipated by the drivers is
approximated as Equation 17:
( I MAX ? ( D – D ) ) + ? x ? I MAX ? ------ ?
2 2 2 2 D
? 12 ?
I IN_RMS = --------------------------------------------------------------------------------------------------------
I MAX
Where:
(EQ. 14)
P = F sw ( 1.5V U Q U + V L Q L ) + P L + P U
Where:
(EQ. 17)
- I MAX is the maximum continuous I LOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor peak-
to-peak ripple amplitude expressed as a percentage of I MAX
(0% to 100%)
- D is the duty cycle that is adjusted to take into account the
-
-
-
-
F sw is the switching frequency of the PWM signal
V U is the upper gate driver bias supply voltage
V L is the lower gate driver bias supply voltage
Q U is the charge to be delivered by the upper driver into the
gate of the MOSFET and discrete capacitors
efficiency of the converter
Duty cycle is written as Equation 15:
- Q L is the charge to be delivered by the lower driver into the
gate of the MOSFET and discrete capacitors
V O
V IN ? EFF
D = --------------------------
13
(EQ. 15)
- P L is the quiescent power consumption of the lower driver
- P U is the quiescent power consumption of the upper driver
FN7974.0
January 26, 2012
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