参数资料
| 型号： | ISL95872HRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 4/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16UTQFN |
| 标准包装： | 3,000 |
| PWM 型： | R4 |
| 输出数： | 1 |
| 频率 - 最大： | 300kHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 16-UFQFN |
| 包装： | 带卷 (TR) |
ISL95872
Ordering Information
PART
TEMP RANGE
PACKAGE
PKG.
PART NUMBER
ISL95872HRUZ-T (Notes 1, 2)
GBT
MARKING
(°C)
-10 to +100
(Pb-Free)
16 Ld 2.6x1.8 UTQFN
DWG. #
L16.2.6x1.8A
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Configuration
ISL95872
(16 LD 2.6X1.8 UTQFN)
Functional Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
TOP VIEW
8
VO
Output voltage sense input for the R4 TM modulator.
The VO pin also serves as the reference input for
the overcurrent detection circuit.
9
PGOOD
Power-good open-drain indicator output. This pin
changes to high impedance when the converter is
able to supply regulated voltage.
GND 1
RTN 2
EN 3
REFIN 4
12 BOOT
11 UGATE
10 PHASE
9 PGOOD
10
11
PHASE
UGATE
Return current path for the UGATE high-side
MOSFET driver, V IN sense input for the R4 TM
modulator, and inductor current polarity detector
input.
High-side MOSFET gate driver output. Connect to
the gate terminal of the high-side MOSFET of the
converter.
12
BOOT
Positive input supply for the UGATE high-side
MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky
boot-strap diode. Connect an MLCC between the
Functional Pin Descriptions
PIN
NUMBER SYMBOL
DESCRIPTION
13
VCC
BOOT pin and the PHASE pin.
Input for the IC bias voltage. Connect +5V to the
VCC pin and decouple with at least a MLCC to the
GND pin.
1
2
3
4
GND
RTN
EN
REFIN
IC ground for bias supply and signal reference.
Negative remote sense input of V OUT . If resistor
divider consisting of R FB and R OFS is used at FB
pin, the same resistor divider should be used at
RTN pin, i.e. keep R FB1 = R FB , and R OFS1 = R OFS .
Enable input for the IC. Pulling EN above the rising
threshold voltage initializes the soft-start sequence.
Input for suppling the external reference voltage
followed by the controller during soft-start.
14
15
16
PVCC
LGATE
PGND
Input for the LGATE and UGATE MOSFET driver
circuits. The PVCC pin is internally connected to the
anode of the Schottky boot-strap diode. Connect
+5V to the PVCC pin and decouple with a MLCC to
the PGND pin.
Low-side MOSFET gate driver output. Connect to
the gate terminal of the low-side MOSFET of the
converter.
Return current path for the LGATE MOSFET driver.
Connect to the source of the low-side MOSFET.
5
6
7
SREF
FB
OCSET
Soft-start and voltage slew-rate programming
capacitor input. Connects internally to the inverting
input of the V SET voltage setpoint amplifier.
Voltage feedback sense input. Connects internally
to the inverting input of the control-loop error
amplifier. The converter is in regulation when the
voltage at the FB pin equals the voltage on the
SREF pin.
Input for the overcurrent detection circuit. The
overcurrent setpoint programming resistor R OCSET
connects from this pin to the sense node.
4
FN7974.0
January 26, 2012
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