参数资料
型号: ISL95872HRUZ-T
厂商: Intersil
文件页数: 14/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16UTQFN
标准包装: 3,000
PWM 型: R4
输出数: 1
频率 - 最大: 300kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 16-UFQFN
包装: 带卷 (TR)
ISL95872
1000
900
800
700
600
500
Q U =100nC
Q L =200nC
Q U =50nC
Q L =100nC
Q U =50nC
Q L =50nC
Q U =20nC
Q L =50nC
Where:
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into saturation
- t OFF is the time required to drive the device into cut-off
400
300
200
100
Layout Considerations
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
0
0
200
400
600
800
1k
1.2k 1.4k 1.6k 1.8k 2k
layer should be adjacent to the signal layer to provide shielding.
The ground plane layer should have an island located under the
FREQUENCY (Hz)
FIGURE 16. POWER DISSIPATION vs FREQUENCY
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain to source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum V DS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFETs switch.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred high-
side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. The preferred low-side MOSFET emphasizes low r DS(ON)
when fully saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as Equation 18:
IC, the components connected to analog or logic signals. The
island should be connected to the rest of the ground plane layer
at one quiet point.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, PGND, PHASE and BOOT.
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. See Figure 17. Input high frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any internal
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
2
(EQ. 18)
planes. Place the components in such a way that the area under
the IC has less noise traces with high dV/dt and di/dt, such as
gate signals and phase node signals.
(EQ. 19)
P CON_HS = I LOAD ? r DS ( ON ) _HS ? D
P SW_HS = ---------------------------------------------------------------------- + ------------------------------------------------------------------
For the high-side MOSFET, (HS), its conduction loss is written as
Equation 19:
2
For the high-side MOSFET, its switching loss is written as Equation
V IN ? I VALLEY ? t ON ? F SW V IN ? I PEAK ? t OFF ? F SW
2 2
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
14
(EQ. 20)
FIGURE 17. TYPICAL POWER COMPONENT PLACEMENT
FN7974.0
January 26, 2012
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