参数资料
| 型号： | ISL98002CRZ-170 |
| 厂商： | Intersil |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC VID DIGITIZER 3CHN AFE 72-QFN |
| 标准包装： | 840 |
| 位数： | 8 |
| 通道数： | 3 |
| 功率（瓦特）： | 535mW |
| 电压 - 电源，模拟： | 3 V ~ 3.6 V |
| 电压 - 电源，数字： | 3 V ~ 3.6 V |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
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20
FN6535.1
December 7, 2009
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to greater than
+900%, causing errors in the output frequency (and
obviously the phase) to change. Subsequent HSYNCs have
the correct, original period, but most analog PLLs will take
dozens of lines to settle back to the correct frequency and
phase after a headswitch disturbance. This causes the top of
the image to “tear” during normal playback. In “trick modes”
(fast forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x1C to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x1C is recommended for all other sync
sources.
PGA
The ISL98002’s Programmable Gain Amplifier (PGA) has a
nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).
The transfer function is calculated in Equation 1:
where GainCode is the value in the Gain register for that
particular color. Note that for a gain of 1V/V, the GainCode
should be 85 (0x55). This is a different center value than the
128 (0x80) value used by some other AFEs, so the firmware
should take this into account when adjusting gains.
The PGAs are updated by the internal clamp signal once per
line. In normal operation, this means that there is a
maximum delay of one HSYNC period between a write to a
Gain register for a particular color and the corresponding
change in that channel’s actual PGA gain. If there is no
regular HSYNC/SOG source, or if the external clamp option
is enabled (register 0x13[5:4]) but there is no external clamp
signal being generated, it may take up to 100ms for a write
to the Gain register to update the PGA. This is not an issue
in normal operation with RGB and YPbPr signals.
Offset DAC
The ISL98002 features a 10-bit Digital-to-Analog Converter
(DAC) per channel to provide extremely fine control over the
full channel offset. The DAC is placed after the PGA to
eliminate interaction between the PGA (controlling
“contrast”) and the Offset DAC (controlling “brightness”).
In normal operation, the Offset DAC is controlled by the
ABLC circuit, ensuring that the offset is always reduced
to sub-LSB levels (see “ABLC” for more information).
When ABLC is enabled, the Offset registers (0x09, 0x0A,
0x0B) control a digital offset added to or subtracted from
the output of the ADC. This mode provides the best image
quality and eliminates the need for any offset calibration.
If desired, ABLC can be disabled (0x17[0] = 1) and the
Offset DAC programmed manually, with the 8 most
significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least
significant bits in register 0x0C[7:2].
The default Offset DAC range is ±127 ADC LSBs. Setting
0x0C[0] = 1 reduces the swing of the Offset DAC by 50%,
making 1 Offset DAC LSB the weight of 1/8th of an ADC
LSB. This provides the finest offset control and applies to
both ABLC and manual modes.
Automatic Black Level Compensation (ABLC)
ABLC is a function that continuously removes all offset
errors from the incoming video signal by monitoring the
offset at the output of the ADC and servoing the 10-bit
analog DAC to force those errors to zero. When ABLC is
enabled, the user offset control is a digital adder, with 8-bit
resolution (see Table 4).
When the ABLC function is enabled (0x17[0] = 0), the
ABLC function is executed every line after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the ABLC
function will be not be triggered while the DPLL is coasting,
Gain
V
----
0.5
GainCode
170
-----------------------------
+
=
(EQ. 1)
TABLE 4. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT
OFFSET
DAC RANGE
0X0C[0]
10-BIT
OFFSET DAC
RESOLUTION
ABLC
0x17[0]
USER OFFSET CONTROL RESOLUTION
USING REGISTERS 0x09 - 0X0B ONLY
(8-BIT OFFSET CONTROL)
USER OFFSET CONTROL RESOLUTION
USING REGISTERS 0X09 - 0x0B AND
0X0C[7:2](10-BIT OFFSET CONTROL)
0
0.25 ADC LSBs
(0.68mV)
0
(ABLC on)
1.0 ADC LSB
(digital offset control)
N/A
1
0.125 ADC LSBs
(0.34mV)
0
(ABLC on)
1.0 ADC LSB
(digital offset control)
N/A
0
0.25 ADC LSBs
(0.68mV)
1
(ABLC off)
1.0 ADC LSB
(analog offset control)
0.25 ADC LSB
(analog offset control)
1
0.125 ADC LSBs
(0.34mV)
1
(ABLC off)
0.5 ADC LSB
(analog offset control)
0.125 ADC LSB
(analog offset control)
ISL98002
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