参数资料
| 型号： | ISL98002CRZ-170 |
| 厂商： | Intersil |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC VID DIGITIZER 3CHN AFE 72-QFN |
| 标准包装： | 840 |
| 位数： | 8 |
| 通道数： | 3 |
| 功率（瓦特）： | 535mW |
| 电压 - 电源，模拟： | 3 V ~ 3.6 V |
| 电压 - 电源，数字： | 3 V ~ 3.6 V |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
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17
FN6535.1
December 7, 2009
requiring that the user do a manual calibration once the
monitor has warmed up.
In addition to drift, many AFEs exhibit interaction between
the offset and gain controls. When the gain is changed, the
magnitude of the offset is changed as well. This again
increases the complexity of the firmware as it tries to
optimize gain and offset settings for a given video input
signal. Instead of adjusting just the offset then the gain, both
have to be adjusted interactively until the desired ADC
output is reached.
The ISL98002 simplifies offset and gain adjustment and
completely eliminates offset drift using its Automatic Black
Level Compensation (ABLC) function. ABLC monitors the
black level and continuously adjusts the ISL98002's 10-bit
offset DACs to null out the offset. Any offset, whether due to
the video source or the ISL98002's analog amplifiers, is
eliminated with 10-bit (1/4 of an ADC LSB) accuracy. Any drift
is compensated for well before it can have a visible effect.
Manual offset adjustment control is still available (an 8-bit
register allows the firmware to adjust the offset ±64 codes) in
exactly 1 ADC LSB increments. Gain is now completely
independent of offset (adjusting the gain no longer affects the
offset) so there is no longer a need to program the firmware to
cope with interactive offset and gain controls.
Finally, there should be no concerns over ABLC itself
introducing visible artifacts; it doesn't. ABLC functions at a
very low frequency, changing the offset in 1/4 LSB
increments, so it can't cause visible brightness fluctuations.
Once ABLC is locked, if the offset doesn't drift, the DACs
won't change. If desired, ABLC can be disabled, allowing
the firmware to work in the traditional way, with 10-bit offset
DACs under the firmware's control.
Gain and Offset Control
To simplify image optimization algorithms, the ISL98002
features fully-independent gain and offset adjustment.
Changing the gain does not affect the DC offset, and the
weight of an offset DAC LSB does not vary depending on the
gain setting.
The full-scale gain is set in the three 8-bit registers
(0x06-0x08). The ISL98002 can accept input signals with
amplitudes ranging from 0.35VP-P to 1.4VP-P.
The offset controls shift the entire RGB input range, changing
the input image brightness. Three separate registers provide
independent control of the R, G, and B channels. Their
nominal setting is 0x80, which forces the ADC to output code
0x00 (or 0x80 for the R (Pr) and B (Pb) channels in YPbPr
mode) during the back porch period when ABLC is enabled.
Functional Description
Inputs
The ISL98002 digitizes analog video inputs in both RGB
and Component (YPbPr) formats, with or without
embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal
to 0V. The range for each color is typically 0V to 0.7V from
black to white. HSYNC and VSYNC are separate signals.
Component YPbPr Inputs
In addition to RGB and RGB with SOG, the ISL98002 has an
option that is compatible with the component YPbPr video
inputs typically generated by DVD players. While the
ISL98002 digitizes signals in these color spaces, it does not
perform color space conversion; if it digitizes an RGB signal,
it outputs digital RGB, while if it digitizes a YPbPr signal, it
outputs digital YCbCr, also called YUV.
The Luminance (Y) signal is applied to the Green Channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
Pb and Pr are bipolar and swing both above and below the
black level. When the YPbPr mode is enabled, the black
level output for the color difference channels shifts to a mid
scale value of 0x80. Setting configuration register
0x05[2] = 1 enables the YPbPr signal processing mode of
operation as shown in Table 1.
The ISL98002 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x18[4] = 1), as shown in Table 2.
There is also a “compatibility mode” (enabled by setting bit 3
of register 0x18 to a 1) that outputs the U and V data with the
format used by the previous generation (“X980xx”) series of
AFEs, shown in Table 3.
TABLE 1. YUV MAPPING (4:4:4)
INPUT
SIGNAL
ISL98002
INPUT
CHANNEL
ISL98002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
U0U1U2U3
Pr
Red
V0V1V2V3
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98002
INPUT
CHANNEL
ISL98002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
driven low
Pr
Red
U0V0U2V2
ISL98002
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