参数资料
型号: ISPPAC-CLK5312S-01T48I
厂商: Lattice Semiconductor Corporation
文件页数: 22/56页
文件大小: 0K
描述: IC BUFFER FANOUT ISP UNIV 48TQFP
标准包装: 250
系列: ispClock™
类型: 时钟发生器,扇出配送,零延迟缓冲器
PLL: 带旁路
输入: HSTL,LVCMOS,LVDS,LVPECL,LVTTL,SSTL
输出: eHSTL,HSTL,LVCMOS,LVTTL,SSTL
电路数: 1
比率 - 输入:输出: 2:12
差分 - 输入:输出: 是/无
频率 - 最大: 267MHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
Lattice Semiconductor
ispClock5300S Family Data Sheet
29
Non Zero Delay Buffer Mode 1
In the non zero delay buffer mode as shown in Figure 24 the output routing matrix completely bypasses the PLL.
Each of the single ended input reference clocks can be routed to any number of available output clocks.
In this mode of operation there is no skew control.
Figure 24. Non Zero Delay Fan Out Buffer Mode 1
O
u
tp
u
tRo
u
ting
Matrix
O
u
tp
u
tRo
u
ting
Matrix
O
u
tp
u
tRo
u
ting
Matrix
Single Ended /
Clock Input
REFA_REFP /
REFB_REFN
PLL Bypassed
ispClock5300S
V1
V3
Single Ended /
Clock Input
REFB_REFN /
REFA_REFP
V2
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ISPPACCLK5312S-01T48I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5312S-01T64C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5312S-01T64I 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5312S-01TN48C 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel
ISPPACCLK5312S-01TN48C 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended