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| 型号： | ISPPAC-CLK5312S-01T48I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 24/56页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER FANOUT ISP UNIV 48TQFP |
| 标准包装： | 250 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
30
ispClock5300 Operating Conguration Summary
The following table summarizes the operating modes of the ispClock5300S.
Note:
Whenever the input buffer is congured as differential input, the fan-out buffer paths become unavailable.
Non-zero delay buffer for differential clock input is realized by using the PLL_BYPASS signal set to logical
‘1’.
Output Skew control mechanism is available only to clock outputs sourced from PLL VCO.
Table 3. ispClock5300S Operating Modes
Thermal Management
In applications where a majority of the ispClock5300S’s outputs are active and operating at or near maximum out-
put frequency, package thermal limitations may need to be considered to ensure a successful design. Thermal
characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Man-
agement which may be obtained at www.latticesemi.com.
The maximum current consumption of the digital and analog core circuitry for ispClock5312S is 150mA worst case
(ICCD + ICCA), and each of the output banks may draw up to 16mA worst case (LVCMOS 3.60V, CL=5pF, fOUT=100
MHz, both outputs in each bank enabled). This results in a total device dissipation:
PDMAX = 3.60V x (6 x 16mA + 150mA) = 0.88W
(3)
With a maximum recommended operating junction temperature (TJOP) of 130°C for an industrial grade device, the
maximum allowable ambient temperature (TAMAX) can be estimated as
TAMAX = TJOP - PDMAX x ΘJA = 130°C - 0.88W x 48°C/W = 85°C
(4)
where ΘJA = 48°C/W for the 48 TQFP package in still air and ΘJA = 42°C/W for the 64 TQFP package in still air.
The above analysis represents the worst-case scenario. Signicant improvement in maximum ambient operating
temperature can be realized with additional cooling. Providing a 200 LFM (Linear Feet per Minute) airow reduces
ΘJA to 44°C/W for the 48 TQFP package.
While it is possible to perform detailed calculations to estimate the maximum ambient operating temperature from
operating conditions, some simpler rule-of-thumb guidance can also be obtained through the derating curves
shown in Figure 25 which shows the maximum ambient operating temperature permitted when operating a given
number of output banks at the maximum output frequency.
ispClock5300S
Operating Mode
Reference Input Clocks
Skew Control
Output Clock
Frequency Divider
Zero Delay Buffer Mode
Single Ended / Differential
Yes
Mixed Zero-Delay &
Non-Zero Delay Buffer Mode
Single Ended Only
Only to Zero Delay
Output Clocks
Only to Zero Delay
Output Clocks
Non-Zero Delay Fan-out Buffer
Mode 1
Single Ended Only
No
Non-Zero Delay Fan-out Buffer
Mode 2
Single Ended / Differential
No
Only to Clocks Sourced From
Bypassed PLL
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5312S-01T48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01T64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01T64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5312S-01TN48C | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5312S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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