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参数资料
| 型号： | IV80C52EXXX-25:RD |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | 1.40 MM HEIGHT, VQFP-44 |
| 文件页数： | 69/134页 |
| 文件大小： | 3805K |
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4
8068U–AVR–06/2013
XMEGA A3
Not recommended for new designs -
Use XMEGA A3U series
3.
Overview
The Atmel
AVR XMEGA A3 is a family of low power, high performance and peripheral rich
CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching
1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Periph-
eral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consump-
tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock for each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Appli-
cation Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a power-
ful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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