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参数资料
| 型号： | K7A163280A-QI16 |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 CACHE SRAM, 3.5 ns, PQFP100 |
| 封装： | 14 X 20 MM, TQFP-100 |
| 文件页数： | 12/18页 |
| 文件大小： | 473K |
| 代理商： | K7A163280A-QI16 |
512Kx36/x32 & 1Mx18 Synchronous SRAM
- 3 -
Rev 0.2
Dec 2001
K7A161880A
K7A163280A
Preliminary
K7A163680A
512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
The K7A163680A, K7A163280A
and K7A161880A are
18,874,368-bit Synchronous Static Random Access Mem-
ory designed for high performance second level cache of
Pentium and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and
integrates address and control registers, a 2-bit burst
address counter and added some new functions for high
performance cache RAM applications; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control sig-
nals.
Burst cycle can be initiated with either the address status
processor(ADSP)
or
address
status
cache
control-
ler(ADSC) inputs. Subsequent burst addresses are gener-
ated internally in the system
′s burst sequence and are
controlled by the burst address advance(ADV) input.
LBO
pin
is
DC
operated
and
determines
burst
sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A163680A, K7A163280A
and K7A161880A are
fabricated using SAMSUNG
′s high performance CMOS
technology and is available in a 100pin TQFP package.
Multiple power and ground pins are utilized to minimize
ground bounce.
GENERAL DESCRIPTION
FEATURES
LOGIC BLOCK DIAGRAM
Synchronous Operation.
2 Stage Pipelined operation with 4 Burst.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
VDD= 1.8V +0.15V/-0.10V Power Supply.
I/O Supply Voltage 1.8V
3V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a linear
burst.
Three Chip Enables for simple depth expansion with No Data Con-
tention ; 2cycle Enable, 1cycle Disable.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A
Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
GW
BW
WEx
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
BURST CONTROL
LOGIC
BURST
512Kx36/x32 , 1Mx18
ADDRESS
CONTROL
OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
BUFFER
LOGIC
C
O
N
T
R
O
L
R
E
G
IS
T
E
R
C
O
N
T
R
O
L
R
E
G
IS
T
E
R
A
′0~A′1
A0~A1
or A2~A19
or A0~A19
REGISTER
FAST ACCESS TIMES
PARAMETER
Symbol
-25
-22
-20
-16
-14
Unit
Cycle Time
tCYC
4.0
4.4
5.0
6.0
7.2
ns
Clock Access Time
tCD
2.6
2.8
3.1
3.5
4.0
ns
Output Enable Access Time
tOE
2.6
2.8
3.1
3.5
4.0
ns
DQPa ~ DQPd
A0~A18
A2~A18
(x=a,b,c,d or a,b)
DQPa,DQPb
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相关代理商/技术参数 |
参数描述 |
|---|---|
| K7A163600A | 制造商:SAMSUNG 制造商全称:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 Synchronous SRAM |
| K7A163600AQC14 | 制造商:Samsung Semiconductor 功能描述: |
| K7A163600A-QC16000 | 制造商:Samsung Semiconductor 功能描述: |
| K7A163600A-QC25000 | 制造商:Samsung Semiconductor 功能描述: |
| K7A163600MQC14 | 制造商:Samsung Semiconductor 功能描述: |
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