参数资料
| 型号： | KAD5510P-50Q72 |
| 厂商： | Intersil |
| 文件页数： | 15/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 500MSPS SGL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 438mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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22
FN6811.2
October 8, 2009
register value then write the incremented or decremented
value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to “Nap/Sleep” on
page 17). This functionality can be overridden and controlled
through the SPI. This is an indexed function when controlled
from the SPI, but a global function when driven from the pin.
This register is not changed by a Soft Reset.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and
resolution of this adjustment are given in Table 11. The
default value of this register after power-up is 80h.
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases.
This is particularly important when multiple ADCs are used in
a time-interleaved system. The phase slip feature allows the
rising edge of the divided clock to be advanced by one input
clock cycle when in CLK/2 mode, as shown in Figure 39.
Execution of a phase_slip command is accomplished by first
writing a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to
bit 0 at address 71h (32 sclk cycles.)
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5510P-50 has a selectable clock divider that can be
set to divide by two or one (no division). By default, the
tri-level CLKDIV pin selects the divisor (refer to “Clock Input
Considerations” on page 26). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5510P-50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive strength
TABLE 8. COARSE GAIN ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
Bit3
+2.8
Bit2
+1.4
Bit1
-2.8
Bit0
-1.4
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 12. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Not Allowed
FIGURE 39. PHASE SLIP: CLK
÷2 MODE, fCLOCK = 1000MHz
CLK
÷
ADC0 CLOCK
SLIP ONCE
ADC0 CLOCK
SLIP TWICE
ADC1 CLOCK
SLIP ONCE
ADC1 CLOCK
SLIP TWICE
ADC0 CLOCK
ADC1 CLOCK
1.00ns
2.00ns
4.00ns
KAD5510P-50
相关PDF资料 |
PDF描述 |
|---|---|
| KAD5512HP-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5512P-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5514P-12Q72 | IC ADC 14BIT 125MSPS SGL 72-QFN |
| KAD5610P-25Q72 | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| KAD5612P-17Q72 | IC ADC 12BIT 170MSPS DUAL 72-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD5512HP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_09 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_0910 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP-12Q48 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| KAD5512HP-12Q72 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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