参数资料
| 型号： | KAD5510P-50Q72 |
| 厂商： | Intersil |
| 文件页数： | 16/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 500MSPS SGL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 438mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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23
FN6811.2
October 8, 2009
in LVDS mode can be set high (3mA) or low (2mA). By
default, the tri-level OUTMODE pin selects the mode and
drive level (refer to “Digital Outputs” on page 17). This
functionality can be overridden and controlled through the
SPI, as shown in Table 13.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 18). This functionality can be overridden
and controlled through the SPI, as shown in Table 14.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or
slow.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 15 shows the
allowable sample rate ranges for the slow and fast settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency
range of the DLL clock generator. The method of setting
these options is different from the other registers.
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with the
desired value for output_mode_B and write that XOR result
to the register.
Device Test
The KAD5510P-50 can produce preset or user defined
patterns on the digital outputs to facilitate in-situ testing. A
static word can be placed on the output bus, or two different
words can alternate. In the alternate mode, the values
defined as Word 1 and Word 2 (as shown in Table 16) are
set on the output bus on alternating clock phases. The test
mode is enabled asynchronously to the sample clock,
therefore several sample clock cycles may elapse before the
data is present on the output bus.
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine
the test pattern in combination with registers 0xC2 through
0xC5. Refer to “” on page 24.
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
TABLE 13. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 14. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
TABLE 15. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
80
200
MSPS
Fast
160
500
MSPS
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
READ
CONFIG_STATUS
0x75
READ
OUTPUT_MODE_B
0x74
DESIRED
VALUE
WRITE TO
0x74
TABLE 16. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST
MODE
WORD 1
WORD 2
0000
Off
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
0110
Reserved
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
KAD5510P-50
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD5512HP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
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| KAD5512HP_0910 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP-12Q48 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| KAD5512HP-12Q72 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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