参数资料
型号: KAD5510P-50Q72
厂商: Intersil
文件页数: 18/29页
文件大小: 0K
描述: IC ADC 10BIT 500MSPS SGL 72-QFN
产品培训模块: High-Speed Analog-to-Digital Converters
标准包装: 1
系列: FemtoCharge™
位数: 10
采样率(每秒): 500M
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 438mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 托盘
输入数目和类型: 1 个差分,单极
25
FN6811.2
October 8, 2009
D
evice
T
est
C0
test_io
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
Output Test Mode [3:0]
00h
G
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
7 = One/Zero
Word Toggle
8 = User Input
9-15 = Reserved
C1
Reserved
00h
G
C2
user_patt 1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt 2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
Reserved
TABLE 17. SPI MEMORY MAP (Continued)
Addr
(Hex)
Parameter
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def. Value
(Hex)
Indexed/
Global
Equivalent Circuits
FIGURE 41. ANALOG INPUTS
FIGURE 42. CLOCK INPUTS
FIGURE 43. TRI-LEVEL DIGITAL INPUTS
FIGURE 44. DIGITAL INPUTS
AVDD
INP
INN
AVDD
F1
F2
F3
F2
F3
CSAMP
1.6pF
CSAMP
1.6pF
TO
CHARGE
PIPELINE
TO
CHARGE
PIPELINE
500O
Ω
Φ
AVDD
CLKP
CLKN
AVDD
TO
CLOCK-
PHASE
GENERATION
11kO
AVDD
18kO
Ω
AVDD
INPUT
AVDD
TO
SENSE
LOGIC
75kO
280O
Ω
INPUT
OVDD
280
Ω
TO
LOGIC
20k
Ω
OVDD
(20k PULL-UP
ON RESETN
ONLY)
KAD5510P-50
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