参数资料
| 型号： | KAD5510P-50Q72 |
| 厂商： | Intersil |
| 文件页数： | 6/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 500MSPS SGL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 10 |
| 采样率（每秒）： | 500M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 438mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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14
FN6811.2
October 8, 2009
Theory of Operation
Functional Description
The KAD5510P-50 is based upon a 10-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 21). The input voltage is
captured by a Sample-Hold Amplifier (SHA) and converted
to a unit of charge. Proprietary charge-domain techniques
are used to successively compare the input to a series of
reference charges. Decisions made during the successive
approximation operations determine the digital code for each
input value. The converter pipeline requires twelve samples
to produce a result. Digital error correction is also applied,
resulting in a total latency of fifteen clock cycles. This is
evident to the user as a latency between the start of a
conversion and the data being available on the digital
outputs.
The device contains two units A/D converters with carefully
matched transfer characteristics. The cores are clocked on
alternate clock edges, resulting in a doubling of the sample
rate. The gain, offset and skew errors between the two unit
ADCs can be adjusted via the SPI port to minimize spurs
associated with the interleaving process.
Time–interleaved ADC systems can exhibit non–ideal
artifacts in the frequency domain if the individual unit ADC
characteristics are not well matched. Gain, offset and timing
skew mismatches are of primary concern.
Gain mismatch results in fundamental image spurs at
fNYQUIST ± fIN. Mismatches in timing skew, which shift the
sampling instances for the two unit ADCs, will result in spurs
in the same locations. Offset mismatches create spurs at DC
and multiples of fNYQUIST.
The design of the KAD5510P-50 minimizes the effect of
process, voltage and temperature variations on the matching
characteristics of the two unit ADCs. The gain and offset of
the two unit ADCs are adjusted after power-on calibration to
minimize the mismatch between the channels. All calibration
is performed using internally generated signals, with the
analog input signal disconnected from the sample and hold
amplifier (SHA).
The KAD5510P-50 does not have the ability to adjust timing
skew mismatches as part of the internal calibration
sequence. Clock routing to each unit ADC is carefully
matched, however some timing skew will exist that may
result in a detectable fundamental image spur at fNYQUIST
±fIN.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration
at start-up. An internal power-on-reset (POR) circuit detects
the supply voltage ramps and initiates the calibration when
the analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibration to execute successfully:
A frequency-stable conversion clock must be applied to
the CLKP/CLKN pins
DNC pins (especially 3, 4 and 18) must not be pulled up or
down
SDO (pin 66) must be high
RESETN (pin 25) must begin low
SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at power-up.
FIGURE 21. ADC CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
LVDS/LVCMOS
OUTPUTS
+
–
KAD5510P-50
相关PDF资料 |
PDF描述 |
|---|---|
| KAD5512HP-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5512P-17Q72 | IC ADC 12BIT 170MSPS SGL 72-QFN |
| KAD5514P-12Q72 | IC ADC 14BIT 125MSPS SGL 72-QFN |
| KAD5610P-25Q72 | IC ADC 10BIT 250MSPS DUAL 72-QFN |
| KAD5612P-17Q72 | IC ADC 12BIT 170MSPS DUAL 72-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KAD5512HP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_09 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP_0910 | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:High Performance 12-Bit, 250/210/170/125MSPS ADC |
| KAD5512HP-12Q48 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| KAD5512HP-12Q72 | 功能描述:模数转换器 - ADC 12-BIT 125MSPS HI PERF SINGLE ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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