参数资料
型号: KAD5612P-17Q72
厂商: Intersil
文件页数: 17/29页
文件大小: 0K
描述: IC ADC 12BIT 170MSPS DUAL 72-QFN
产品培训模块: High-Speed Analog-to-Digital Converters
标准包装: 1
系列: FemtoCharge™
位数: 12
采样率(每秒): 170M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 405mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 托盘
输入数目和类型: 2 个差分,单极
24
FN6803.2
September 9, 2009
SPI Memory Map
TABLE 17. SPI MEMORY MAP
ADDR
(Hex)
PARAMETER
NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF.
VALUE
(Hex)
INDEXED/
GLOBAL
SPI
Config
00
port_config
SDO
Active
LSB First
Soft
Reset
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
00h
G
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
00h
G
03-07
reserved
Reserved
Info
08
chip_id
Chip ID #
Read only
G
09
chip_version
Chip Version #
Read only
G
In
dexe
d
Devic
e
Con
fig
/Con
trol
10
device_index_A
Reserved
ADC01
ADC00
00h
I
11-1F
reserved
Reserved
20
offset_coarse
Coarse Offset
cal. value
I
21
offset_fine
Fine Offset
cal. value
I
22
gain_coarse
Reserved
Coarse Gain
cal. value
I
23
gain_medium
Medium Gain
cal. value
I
24
gain_fine
Fine Gain
cal. value
I
25
modes
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
00h
NOT
affected by
Soft Reset
I
26-5F
reserved
Reserved
60-6F
reserved
Reserved
Glo
b
al
D
evice
Co
nf
ig/Co
n
tr
o
l
70
skew_diff
Differential Skew
80h
G
71
phase_slip
Reserved
Next
Clock
Edge
00h
G
72
clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
G
73
output_mode_A
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
74
output_mode_B
DLL Range
0 = fast
1 = slow
00h
NOT
affected by
Soft Reset
G
75
config_status
XOR
Result
Read Only
G
76-BF
reserved
Reserved
KAD5612P
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