参数资料
| 型号： | KAD5612P-17Q72 |
| 厂商： | Intersil |
| 文件页数： | 21/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 170MSPS DUAL 72-QFN |
| 产品培训模块： | High-Speed Analog-to-Digital Converters |
| 标准包装： | 1 |
| 系列： | FemtoCharge™ |
| 位数： | 12 |
| 采样率（每秒）： | 170M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 405mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个差分，单极 |
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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FN6803.2
September 9, 2009
Revision History
DATE
REVISION
CHANGE
7/30/08
Rev 1
Initial Release of Production Datasheet
12/5/08
FN6803.0 Converted to intersil template. Assigned file number FN6803. Rev 0 - first release with new file number.
1/21/09
FN6803.1 P1; revised Key Specs
P2; added Part Marking column to Order Info
P4; Moved Thermal Impedance under Thermal Info (used to be on p. 7). Added Theta JA Note 2.
P4-7; edits throughout the Specs table. Added Notes 8 and 9. Revised Notes 6 and 7.
P7; Removed ESD section
P10-12; revised Performance Curves throughout
P14; User Inititated Reset section; revised 2nd sentence of 1st paragraph
P18; SPI Physical Interface; revised 3nd sentence of 1st paragraph. “SPI Physical Interface”; revised 2nd sentence of
4th paragraph.
P20; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised Table 8
P21; revised last 2 sentence of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of "PHASE SLIP: CLK÷2 MODE,
fCLOCK = 500MHz"
P24; revised Figure 44
P24; Table 17; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
5/07/09
8/4/09
FN6803.2 1) Updated pin diagram; Added nap mode, sleep mode wake up times to spec table
2) Added CSB,SCLK Setup time specs for nap, sleep modes to spec table
4) Changed SPI setup spec wording in spec table
5) Change to pin description table for clarification
6) Added thermal pad note
8) Update multiple device usage note on at “SPI Physical Interface” on page 19
9) Added ‘Reserved’ to SPI memory map at address 25H
10) Added section on “ADC Evaluation Platform” on page 26
11) Intersil Standards: Added Pb-free reflow link to thermal information, moved caution statement above note to follow
format, added note reference for over-temp note in Elec Spec Tables and added over-temp note at end of table, updated
Table of Contents.
1. Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs
3. Updated wakeup time description in “Nap/Sleep” on page 17.
4. Removed calibration note in spec table
8/21/09
1. Fig 43.changed 2 resistors between inputs from 11 ohms to 11k ohms.
2. Fig 45. moved 20k ohm label upwards a bit
3. Page 15, reword the end of the paragraph above Figure 24
4. Changed tDHR spec on p7 from 1.5cycles to 3 cycles.
KAD5612P
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