参数资料
型号: KAD5612P-17Q72
厂商: Intersil
文件页数: 28/29页
文件大小: 0K
描述: IC ADC 12BIT 170MSPS DUAL 72-QFN
产品培训模块: High-Speed Analog-to-Digital Converters
标准包装: 1
系列: FemtoCharge™
位数: 12
采样率(每秒): 170M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 405mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 托盘
输入数目和类型: 2 个差分,单极
8
FN6803.2
September 9, 2009
Pinout/Package Information
Pin Descriptions
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 6, 19, 24, 71
AVDD
1.8V Analog Supply
2-5, 17, 18, 28-31
DNC
Do Not Connect
7, 10-12, 72
AVSS
Analog Ground
8, 9
BINP, BINN
B-Channel Analog Input Positive, Negative
13, 14
AINN, AINP
A-Channel Analog Input Negative, Positive
15
VCM
Common Mode Output
16
CLKDIV
Clock Divider Control
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, see “User-Initiated Reset” on page 15)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
33
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0]
34
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
35
D1P
[D1]
LVDS Bit 1 Output True
[LVCMOS Bit 1]
37
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
38
D2P
[D2]
LVDS Bit 2 Output True
[LVCMOS Bit 2]
39
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
40
D3P
[D3]
LVDS Bit 3 Output True
[LVCMOS Bit 3]
41
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
42
D4P
[D4]
LVDS Bit 4 Output True
[LVCMOS Bit 4]
43
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
44
D5P
[D5]
LVDS Bit 5 Output True
[LVCMOS Bit 5]
46
RLVDS
LVDS Bias Resistor (connect to OVSS with a 10k
Ω, 1% resistor)
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
49
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
KAD5612P
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