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参数资料
| 型号： | KFM4GH6Q4M-DEB80 |
| 元件分类： | PROM |
| 英文描述： | 256M X 16 FLASH 1.8V PROM, 70 ns, PBGA63 |
| 封装： | 10 X 13 MM, 1 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, FBGA-63 |
| 文件页数： | 4/142页 |
| 文件大小： | 2226K |
| 代理商： | KFM4GH6Q4M-DEB80 |
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Flex-MuxOneNAND4G(KFM4GH6Q4M-DEBx)
- 101 -
FLASH MEMORY
Flex-MuxOneNAND8G(KFN8GH6Q4M-DEBx)
Flex-MuxOneNAND16G(KFKAGH6Q4M-DEBx)
3.13.5 OTP and 1st Block OTP Lock Operation
OTP and 1st Block can be locked simultaneously, for locking bit lies in the same word of OTP area.
1st Block OTP can be accessed just as any other NAND Flash Array Blocks before it is locked, however, once 1st Block is locked to be OTP,
1st Block OTP cannot be erased or programmed. Also, OTP area can only be programmed once without erase capability, it can be locked
when the device starts up to prevent any changes from being made.
Locking the OTP and 1st Block OTP
Programming to the OTP area and 1st Block OTP area can be prevented by locking the OTP area. Locking the OTP area is
accomplished by programming XXF0h to the 1st word of sector4 of main of the page49 memory area in the OTP block.
At device power-up, this word location is checked and if XXF0h is found, the OTPL and OTPBL bit of the Controller Status Register is set to "1",
indicating the OTP and 1st Block is locked. When the Program Operation finds that the status of the OTP and 1st Block is locked, the device
updates the Error Bit of the Controller Status Register as "1" (fail).
OTP and 1st Block OTP simultaneous Lock Operation Steps
Issue the OTP Access Command
Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and
"Write Program" commands)
Write ‘XXF0h’ data into the 1st word of sector4 of main of the page49 memory area of the DataRAM.
Issue a Flash Block Address (FBA) which is 0000h of NAND Flash Array address map.
Issue a Program command to program the data from the DataRAM into the OTP
When the 1st Block OTP lock is complete, do a Cold Reset to exit the OTP Access mode
and update 1st Block OTP lock bit[5] and OTP lock bit[6].
1st Block OTP lock bit[5] and OTP lock bit[6] of the Controller Status Register will be set to "1" and
the OTP and 1st Block will be locked.
Unlike other remaining main area of the NAND Flash Array memory, once the OTP block and the 1st block OTP are locked, it cannot be
unlocked.
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