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| 型号： | KIT33886DHEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC33886 H-BRIDGE |
| 标准包装： | 1 |
| 主要目的： | 电源管理，H 桥驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33886 |
| 主要属性： | 5?V ~ 40?V 电源，5A 输出 |
| 次要属性： | 短路、热和欠压保护 |
| 已供物品： | 板，CD |
| 相关产品： | MC33886VWR2-ND - IC H-BRIDGE 5.0A 20-HSOP MC33886DHR2-ND - IC H-BRIDGE 5.0A 20-HSOP MC33886VW-ND - IC H-BRIDGE 5.0A OUTPUT 20-HSOP MC33886DH-ND - IC H-BRIDGE 5.0A OUTPUT 20-HSOP |
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5.0 A H-BRIDGE
THERMAL ADDENDUM - REVISION 2.0
5.0 A H-BRIDGE
33886HSOP
THERMAL ADDENDUM - REVISION 2.0
Introduction
This thermal addendum is provided as a supplement to the MC33186 technical
20-PIN HSOP-EP
data sheet. The addendum provides thermal performance information that may
be critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the data sheet.
Packaging and Thermal Considerations
The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.
There is a single heat source (P), a single junction temperature (T J ), and thermal
resistance (R ? JA ).
VW (Pb-FREE) SUFFIX
T J
=
R ? JA
.
P
98ASH70702A
20-PIN HSOP-EP
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not
meant to and will not predict the performance of a package in an application-
specific environment. Stated values were obtained by measurement and
simulation according to the standards listed below.
Standards
Note For package dimensions, refer to
the 33886 device data sheet.
Table 7.
Thermal Performance Comparison
Thermal Resistance
R ? JA (1)(2)
?? C/W]
20
1.0
1.0
R ? JB (2)(3)
R ? JA (1)(4)
6.0
52
0.2
0.2
R ? JC
1.0
* All measurements
are in millimeters
NOTES:
1.Per JEDEC JESD51-2 at natural convection, still air condition.
2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7.
Soldermast
openings
3.Per JEDEC JESD51-8, with the board temperature on the center
trace near the center lead.
20 Terminal HSOP-EP
1.27 mm Pitch
Thermal vias
connected to top
buried plane
4.Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5.Thermal resistance between the die junction and the exposed
pad surface; cold plate attached to the package bottom side,
remaining surfaces insulated.
16.0 mm x 11.0 mm Body
12.2 mm x 6.9 mm Exposed Pad
Figure 24. Thermal Land Pattern for Direct Thermal
Attachment According to JESD51-5
33886
Analog Integrated Circuit Device Data ?
24
Freescale Semiconductor
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