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参数资料
| 型号： | KIT33886DHEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC33886 H-BRIDGE |
| 标准包装： | 1 |
| 主要目的： | 电源管理，H 桥驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33886 |
| 主要属性： | 5?V ~ 40?V 电源，5A 输出 |
| 次要属性： | 短路、热和欠压保护 |
| 已供物品： | 板，CD |
| 相关产品： | MC33886VWR2-ND - IC H-BRIDGE 5.0A 20-HSOP MC33886DHR2-ND - IC H-BRIDGE 5.0A 20-HSOP MC33886VW-ND - IC H-BRIDGE 5.0A OUTPUT 20-HSOP MC33886DH-ND - IC H-BRIDGE 5.0A OUTPUT 20-HSOP |
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V ? V+ ? 28 V and -40 ? C ? T A ? 125 ? C, unless otherwise noted. Typical values noted
reflect the approximate parameter mean at T A = 25 ? C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency (20)
f PWM
–
–
10
kHz
Maximum Switching Frequency During Active Current Limiting
f MAX
–
–
20
kHz
Output ON Delay (22)
t d (ON)
? s
V+ = 14 V
Output OFF Delay (22)
V+ = 14 V
t D (OFF)
–
–
–
–
18
18
? s
Output Rise and Fall Time
t F , t R
? s
V+ = 14 V, I OUT = 3.0 A
2.0
5.0
8.0
Output Latch-OFF Time
Output Blanking Time
Output FET Body Diode Reverse Recovery Time (24)
t A
t B
t RR
15
12
100
20.5
16.5
–
26
21
–
? s
? s
ns
Disable Delay Time
t D (DISABLE)
–
–
8.0
? s
Short-circuit / Overtemperature Turn- OFF Time (26)
Power-OFF Delay Time
t FAULT
t POD
–
–
4.0
1.0
–
5.0
? s
ms
Notes
20. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM
pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching
frequency. Refer to Typical Switching Waveforms, Figures 10 through 17 , pp. 11–12 .
21. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant
OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency.
22. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition
direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the
90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to
23. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6 , page 9 .
24. Parameter is guaranteed by design but not production tested.
25. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See
26. Increasing currents will become limited at I LIM . Hard shorts will breach the I SCH or I SCL limit, forcing the output into an immediate tri-
state latch-OFF. See Figures 8 and 9 , page 10 . Active current limiting will cause junction temperatures to rise. A junction temperature
above 160 ? C will cause the active current limiting to progressively “fold-back” (or decrease) to 2.5 A typical at 175 ? C where thermal
33886
Analog Integrated Circuit Device Data ?
8
Freescale Semiconductor
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