参数资料
型号: KMC8113TMP3600V
厂商: Freescale Semiconductor
文件页数: 10/44页
文件大小: 0K
描述: IC DSP 300/400MHZ 431FCPGA
标准包装: 2
系列: StarCore
类型: SC140 内核
接口: 以太网,I²C,TDM,UART
时钟速率: 300MHz
非易失内存: 外部
芯片上RAM: 1.436MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.10V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 431-BFBGA,FCBGA
供应商设备封装: 431-FCPBGA(20x20)
包装: 托盘
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Electrical Characteristics
Freescale Semiconductor
18
2.5.4
Reset Timing
The MSC8113 has several inputs to the reset logic:
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
Bus monitor reset
Host reset command through JTAG
All MSC8113 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 10 describes the reset sources.
Internal bus frequency (BLCK)
100/133
DSI clock frequency (HCLKIN)
Core frequency = 300 MHz
Core frequency = 400 MHz
HCLKIN
≤ (min{70 MHz, CLKOUT})
HCLKIN
≤ (min{100 MHz, CLKOUT})
External clock frequency (CLKIN or CLKOUT)
100/133
Table 8. Clock Frequencies
Characteristics
Symbol
300 MHz Device
400 MHz Device
MinMax
CLKIN frequency
FCLKIN
20
100
20
133.3
BCLK frequency
FBCLK
40
100
40
133.3
Reference clock (REFCLK) frequency
FREFCLK
40
100
40
133.3
Output clock (CLKOUT) frequency
FCLKOUT
40
100
40
133.3
SC140 core clock frequency
FCORE
200
300
200
400
Note:
The rise and fall time of external clocks should be 3 ns maximum
Table 9. System Clock Parameters
Characteristic
Min
Max
Unit
Phase jitter between BCLK and CLKIN
0.3
ns
CLKIN frequency
20
MHz
CLKIN slope
—3
ns
PLL input clock (after predivider)
20
100
MHz
PLL output frequency (VCO output)
300 MHz core
400 MHz core
800
1200
1600
MHz
CLKOUT frequency jitter1
200
ps
CLKOUT phase jitter1 with CLKIN phase jitter of ±100 ps.
500
ps
Notes:
1.
Peak-to-peak.
2.
Not tested. Guaranteed by design.
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
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