参数资料
型号: KMC8113TMP3600V
厂商: Freescale Semiconductor
文件页数: 9/44页
文件大小: 0K
描述: IC DSP 300/400MHZ 431FCPGA
标准包装: 2
系列: StarCore
类型: SC140 内核
接口: 以太网,I²C,TDM,UART
时钟速率: 300MHz
非易失内存: 外部
芯片上RAM: 1.436MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.10V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 431-BFBGA,FCBGA
供应商设备封装: 431-FCPBGA(20x20)
包装: 托盘
Electrical Characteristics
MSC8113 Tri-Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
17
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
1.
During time interval A, VDDH should always be equal to or less than the VDD/VCCSYN voltage level.
The duration of interval A should be kept below 10 ms.
2.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
2.5.3
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user must ensure that maximum
frequency values are not exceeded.
Figure 7. Start-Up Sequence: VDD Raised Before VDDH with CLKIN Started with VDDH
Figure 8. Power-Up Sequence for VDDH and VDD/VCCSYN
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
Core frequency
300/400
Reference frequency (REFCLK)
100/133
Vo
lt
a
g
e
Time
o.5 V
3.3 V
1.1 V
VDDH Nominal
PORESET/TRST asserted
VDD Nominal
CLKIN starts toggling
VDD applied
PORESET/TRST deasserted
1
VDDH applied
VDDH = Nominal
VDD = Nominal
3.3 V
1.2 V
A
B
VDD/VCCSYN
VDDH (IO)
t (time)
V
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