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| 型号： | KMC8144SVT1000B |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 79/80页 |
| 文件大小： | 0K |
| 描述： | IC DSP 783FCPBGA |
| 标准包装： | 2 |
| 系列： | StarCore |
| 类型： | SC3400 内核 |
| 接口： | EBI/EMI，以太网，I²C，PCI，Serial RapidIO，SPI，TDM，UART，UTOPIA |
| 时钟速率： | 1.0GHz |
| 非易失内存： | ROM（96 kB） |
| 芯片上RAM： | 10.5MB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.00V |
| 工作温度： | 0°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 783-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
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Revision History
Table 66. Document Revision History (continued)
Rev.
Date
Description
7
Dec 2007
?
?
?
?
Changed minimum voltage level for V DDM3 to 1.213 (1.25 – 3%) in Table 3 .
Added POS to titles in Section 2.6.6 .
Added additional signals to titles in Section 2.6.8 . Added high and low voltage ranges to Table 19 .
Added ATM and POS to headings in Section 2.7.11 . Changed characteristics to generic input/output in Table 52 ,
Figure 33 , and Figure 34 .
? Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13 , Asynchronous Signal Timing . Renumbered
subsequent sections, tables, and figures.
? Added POS to all UTOPIA references in Section 3.4.5 .
8
9
10
Dec 2007
Mar 2008
Apr 2008
? Changed GCR4 program value to 0x0004C130 in Note 7 in Table 51 .
? Changed description of Table 20 in Section 2.7.2 .
? Added 3 to the PLL supply voltage row in Table 2 .
? Changed the first sentence in Section 3.4.8 to reflect that Table 70 indicates what to do with pins if they are
“not” required by the design. Changed the Pin Connection for GPIO[0–31] to GND.
? Updated ordering information in Section 4 .
? Multiple corrections of minor punctuation errors.
11
Aug 2008
?
?
?
?
?
Removed the comment about preliminary estimates before Table 4 and removed non-DDR rows in the table.
Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables renumbered.
Added a note to Table 15 to exclude TDM and TMS. Removed reference to overshoot and undershoot and
associated figure.
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
Changed minimum clock frequency to 33 MHz and maximum clock frequency to 133 MHz in Table 16 .
Deleted old Table 17 Clock Parameters.
Changed minimum input clock frequency to 33 MHz in Table 19 .
Changed the t DDKHAX minimum value in Table 23 to 1.85 ns.
Removed t REFPJ and t REFCJ from Table 24 because the specifications are not required or tested.
Removed t PCRSTCLK , t PCRSTOFF , t PCRST , and t PCRHFA from Table 36 because the specifications are not required
or tested.
Removed t UAVKH and t UAVXH from Table 38 because the specifications are not required or tested.
The parameters t MDCH , t MDCR , and t MDHF were removed from Table 40 because the specifications are not
required or tested.
The parameters t MTXH /t MTX , t MTXR , and t MTXF were removed from Table 41 because the specifications are not
required or tested.
The parameters t MRXH /t MRX , t MRXR , and t MRXF were removed from Table 42 because the specifications are not
required or tested.
The parameters t RMXH /t RMX , t RMXR , and t RMXF were removed from Table 43 because the specifications are not
required or tested.
Removed the parameters t RGT , t RGTH /t RGT (1000Base-T), t RGTH /t RGT (10Base-T), t RGTR , t RGTF , t G12 , and
t G125H /t G125 were removed from Table 45 and Table 46 because the specifications are not required or tested.
Changed t UEKHOX to guaranteed by design in Table 47 .
Updated Figure 35 and Figure 36 SPI timing diagrams.
12
13
Aug 2008
Feb 2009
?
?
?
?
Changed b8t to bit in the M3 memory description on the first page.
Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of Table 14 .
In Figure 31 , for GTX_CLK, changed (at transmitter) to (at DSP) and for RX_CLK, changed (at PHY) to (at
DSP).
?
Updated package drawing to the latest revision, Case No. 1842-04 in Figure 44 .
14
15
16
Jul 2009
Nov 2009
May 2010
? Updated MV REF equations and temperature ranges in Table 3 .
? Updated Core and PLL input voltage tolerance in Table 3 .
? Corrected typo in Table 23 . Changed MCLK minimum time to 5 ns.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
79
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| KMC8144SVT800A | 功能描述:数字信号处理器和控制器 - DSP, DSC PACSUN SAMPLE PART RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| KMC8144SVT800B | 功能描述:IC DSP 783FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| KMC8144TVT1000A | 功能描述:数字信号处理器和控制器 - DSP, DSC PACSUN SAMPLE PART RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| KMC8144TVT1000B | 功能描述:IC DSP 783FCPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:StarCore 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| KMC8144TVT800A | 功能描述:数字信号处理器和控制器 - DSP, DSC PACSUN SAMPLE PART RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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