参数资料
型号: KMC8144TVT1000A
厂商: Freescale Semiconductor
文件页数: 35/80页
文件大小: 0K
描述: IC DSP 783FCPBGA
标准包装: 2
系列: StarCore
类型: SC3400 内核
接口: EBI/EMI,以太网,I²C,PCI,Serial RapidIO,SPI,TDM,UART,UTOPIA
时钟速率: 1.0GHz
非易失内存: ROM(96 kB)
芯片上RAM: 10.5MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.00V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.
2.6.1
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.2
describes the clocking characteristics. Section 2.6.3 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8144 device:
?
Note:
?
?
PORESET and TRST must be asserted externally for the duration of the power-up sequence using the V DDIO (3.3 V)
supply. See Table 19 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.
During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.
For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the
V DDM3IO (2.5 V) supply. See Section 3.1.1 , Power-on Sequence for additional design information.
CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation
(see Figure 6 ). 32 cycles should be accounted only after V DDIO reaches its nominal value.
CLKIN and PCI_CLK_IN should either be stable low during the power-up of V DDIO supply and start their swings after
power-up or should swing within V DDIO range during V DDIO power-up., so their amplitude grows as V DDIO grows
during power-up.
Figure 6 shows a sequence in which V DDIO is raised after V DD and CLKIN begins to toggle with the raise of V DDIO supply.
V DDIO = Nominal
V DD = Nominal
1
3.3 V
1.0 V
V DDIO Nominal
V DD Nominal
Time
PORESET/TRST asserted
V DD applied
CLKIN starts toggling
PORESET
V DDIO applied
Figure 6. Start-Up Sequence with V DD Raised Before V DDIO with CLKIN Started with V DDIO
2.6.2
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 16 shows the maximum frequency values for
CLKIN and PCI_CLK_IN. The user must ensure that maximum frequency values are not exceeded.
Table 16. Clock Frequencies
CLKIN frequency
PCI_CLK_IN frequency
CLKIN duty cycle
PCI_CLK_IN duty cycle
Characteristic
Symbol
F CLKIN
F PCI_CLK_IN
D CLKIN
D PCI_CLK_IN
Min
33
33
40
40
Max
133
133
60
60
Unit
MHz
MHz
%
%
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
35
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