参数资料
型号: KMC8144VT800B
厂商: Freescale Semiconductor
文件页数: 61/80页
文件大小: 0K
描述: IC DSP 783FCPBGA
标准包装: 2
系列: StarCore
类型: SC3400 内核
接口: EBI/EMI,以太网,I²C,PCI,Serial RapidIO,SPI,TDM,UART,UTOPIA
时钟速率: 800MHz
非易失内存: ROM(96 kB)
芯片上RAM: 10.5MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.00V
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
2.6.12
SPI Timing
Table 48 lists the SPI input and output AC timing specifications.
Table 48. SPI AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs valid—Master mode (internal clock) delay
SPI outputs hold—Master mode (internal clock) delay
SPI outputs valid—Slave mode (external clock) delay
SPI outputs hold—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock input) setup time
SPI inputs—Master mode (internal clock) input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
t NIKHOV
t NIKHOX
t NEKHOV
t NEKHOX
t NIIVKH
t NIIXKH
t NEIVKH
t NEIXKH
0.5
2
4
0
4
2
6
8
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1.
2.
Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.
The symbols for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and
t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t NIKHOX symbolizes the internal timing (NI) for
the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
Figure 34 provides the AC test load for the SPI.
Output
Z 0 = 50 Ω
R L = 50 Ω
OV DD /2
Figure 34. SPI AC Test Load
Figure 35 and Figure 36 represent the AC timings from Table 48 . Note that although the specifications generally reference the
rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.
Figure 35 shows the SPI timings in slave mode (external clock).
SPICLK (Input)
Input Signals:
SPIMOSI
t NEIVKH
t NEIXKH
(See Note)
Output Signals:
t NIKHOX
t NIKHOV
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 35. SPI AC Timing in Slave Mode (External Clock)
Figure 36 shows the SPI timings in master mode (internal clock).
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
61
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