参数资料
型号: KMC8144VT800B
厂商: Freescale Semiconductor
文件页数: 67/80页
文件大小: 0K
描述: IC DSP 783FCPBGA
标准包装: 2
系列: StarCore
类型: SC3400 内核
接口: EBI/EMI,以太网,I²C,PCI,Serial RapidIO,SPI,TDM,UART,UTOPIA
时钟速率: 800MHz
非易失内存: ROM(96 kB)
芯片上RAM: 10.5MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.00V
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
Hardware Design Considerations
3.3
Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
?
?
Note:
3.4
Note:
Keep clock and timing signal paths as short as possible and route with 50 Ω impedance.
Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.
Connectivity Guidelines
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
2.
3.
4.
5.
Note:
3.4.1
GND indicates using a 10 k Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
V DD indicates using a 10 k Ω pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
NC indicates “not connected” and means do not connect anything to the pin.
The phrase “in use” indicates a typical pin connection for the required function.
Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of
subset interface connection.
DDR Memory Related Pins
This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.
Note:
For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines
of strobes in DDR1), please refer to Table 51 .
3.4.1.1
DDR Interface Is Not Used
Table 51. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
MDQ[0–31]
MDQS[0–3]
MDQS[0–3]
MA[0–15]
MCK[0–2]
MCK[0–2]
MCS[0–1]
Signal Name
Pin Connection
NC
NC
NC
NC
NC
NC
NC
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
67
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