参数资料
型号: KMSC7119VM1200
厂商: Freescale Semiconductor
文件页数: 37/60页
文件大小: 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
标准包装: 2
系列: StarCore
类型: 定点
接口: 主机接口,I²C,UART
时钟速率: 300MHz
非易失内存: ROM(8 kB)
芯片上RAM: 464kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 400-LFBGA
供应商设备封装: 400-MAPBGA(17x17)
包装: 托盘
MSC7119 Data Sheet, Rev. 8
Hardware Design Considerations
Freescale Semiconductor
42
3.2
This section outlines the MSC7119 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1
Power Supply
The MSC7119 requires four input voltages, as shown in Table 32.
You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2
Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note:
There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
Table 32. MSC7119 Voltages
Voltage
Symbol
Value
Core
VDDC
1.2 V
Memory
VDDM
2.5 V
Reference
VREF
1.25 V
I/O
VDDIO
3.3 V
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