参数资料
型号: KSZ8695PX-EVAL
厂商: Micrel Inc
文件页数: 23/40页
文件大小: 0K
描述: KIT EVAL KSZ8695PX EXPERIMENT
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8695PX
主要属性: 单芯片网关解决方案
已供物品:
相关产品: 576-1024-ND - IC SWITCH 10/100 1PORT 289PBGA
其它名称: 576-3876
KSZ8695PX-EVAL-ND
KS8695PX
Signal Descriptions by Group
Micrel
Clock and Reset Pins
Pin Name
I/O Type (1)
Description
E1
E2
M15
A17
U17
T17
XCLK1/
CPUCLK
XCLK2
URTSN/
CPUCLKSEL
RESETN
WRSTO
EROEN/
WRSTPLS
I
I
O/I
I
O
O/I
External Clock In. This signal is used as the source clock for the transmit clock of the
internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
KS8695PX chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695PX. When in the reset state, all the output pins are
tri-stated and all open drain signals are ? oating.
Watchdog timer reset output. This signal is asserted for at least 200ms if
RESETN is asserted or when the internal watchdog timer expires.
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low. When
asserted, this signal controls the output enable port of the speci? ed device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin Name
I/O Type (1)
Description
G14
G15
F14
F15
F16
TCK
TMS
TDI
TDO
TRSTN
I
I
I
O
I
JTAG test clock.
JTAG test mode select.
JTAG test data in.
JTAG test data out.
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin Name I/O Type (1) Description
G1
G2
G3
G4
G5
WANTXP
WANTXM
WANRXP
WANRXM
WANFXSD
O
O
I
I
I
WAN PHY transmit signal + (differential).
WAN PHY transmit signal – (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal – (differential).
WAN ? ber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb ? ber mode. See Application Note 10.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
M9999-091605
23
September 2005
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