参数资料
型号: KSZ8695PX-EVAL
厂商: Micrel Inc
文件页数: 26/40页
文件大小: 0K
描述: KIT EVAL KSZ8695PX EXPERIMENT
标准包装: 1
主要目的: 接口,以太网控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8695PX
主要属性: 单芯片网关解决方案
已供物品:
相关产品: 576-1024-ND - IC SWITCH 10/100 1PORT 289PBGA
其它名称: 576-3876
KSZ8695PX-EVAL-ND
KS8695PX
General Purpose I/O Pins (continued)
Pin Name I/O Type (1) Description
Micrel
D4
C2
C3
C4
B2
B3
B4
A4
D5
B5
C5
A5
D6
B6
C6
B7
C7
A7
D8
B8
D9
A8
C9
D12
B12
C12
A12
D13
B13
C13
A13
B14
C14
A14
D15
B15
PCLK
NC
NC
GNT1N
NC
NC
REQ1N
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
I
O
I
I/O
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
use the system PCI clock to drive this input.
No Connect
No Connect
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
guest bridge mode, this signal is an output to indicate that the KS8695PX is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
basically the KS8695PX’s request output.
No Connect
No Connect
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this is an input
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
this is basically the KS8695PX's grant input.
32-Bit PCI address and data. PCI bus transactions consist of an address
phase followed by one or more data phases. Address and data signals are multi-
plexed on the same pins. For a PCI write transaction, the source of the data is the
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX supports both read and write burst transactions. In the case of a read
transaction, a special data turn around cycle is needed between the address phase
and the data phase(s).
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
September 2005
26
M9999-091605
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