参数资料
| 型号： | KSZ8695PX-EVAL |
| 厂商： | Micrel Inc |
| 文件页数： | 27/40页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL KSZ8695PX EXPERIMENT |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ8695PX |
| 主要属性： | 单芯片网关解决方案 |
| 已供物品： | 板 |
| 相关产品： | 576-1024-ND - IC SWITCH 10/100 1PORT 289PBGA |
| 其它名称： | 576-3876 KSZ8695PX-EVAL-ND |
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KS8695PX
General Purpose I/O Pins (continued)
Pin Name I/O Type (1) Description
Micrel
C15
A15
A16
A6
B9
A11
D14
C8
D10
A9
C10
C11
D7
D11
B11
A10
E4
PAD2
PAD1
PAD0
CBEN3
CBEN2
CBEN1
CBEN0
PAR
FRAMEN
IRDYN
TRDYN
DEVSELN
IDSEL
STOPN
PERRN
SERRN
M66EN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I
32-Bit PCI address and data (continued from previous page).
PCI commands and byte enable. Active low.
The PCI command and byte enable signals are multiplexed on the same pins. During
the ? rst clock cycle of a PCI transaction, the CBEN bus contains the command for
the transaction. The PCI transaction consists of the address phases and one or more
data phases. During the data phases of the transaction, the bus carries the byte
enable for the current data phases.
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695PX
generates PAR during the address phase and write data phases as a bus master and
during read data phases as a target. It checks for correct PAR during the read data
phase as a bus master, during every address phase as a bus slave, and during write
data phases as a target.
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase, and
deasserted before the ? nal transfer of the data phase of the transaction.
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write transaction.
During a read transaction, it indicates that the master is ready to accept data from the
target. A target monitors the IRDYN signal when a data phase is completed on any
rising edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles
are inserted until both IRDYN and TRDYN are asserted together.
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
PCI device select signal. Active low. This signal is asserted when the KS8695PX is
selected as a target during a bus transaction. When the KS8695PX is the initiator of
the current bus access, it expects the target to assert DEVSELN within ? ve PCI bus
cycles, con? rming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695PX aborts the bus cycle. To meet the timing require-
ment, the KS8695PX asserts this signal in a medium speed decode timing. ( two bus
cycles).
Initialization device select. Active high. It is used as a chip select during con? gura-
tion read and write transactions.
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695PX responds
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
abort the transaction.
PCI parity error signal. Active low. The KS8695PX asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695PX
monitors for any reported parity error on PERRN. When the KS8695PX is the bus
master and a parity error is detected, the KS8695PX sets error bits in the control
status registers. It completes the current data burst transaction, and then stops the
operation. After the host clears the system error, the KS8695PX continues its
operation.
PCI system error signal. Active low. If an address parity error is detected, the
KS8695PX asserts the SERRN signal two clocks after the failing address.
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK is
driven by an external host bridge.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
M9999-091605
27
September 2005
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| KSZ8695X | 功能描述:网络控制器与处理器 IC Integrated Multi-Port Gateway Solution (Lead Free) RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| KSZ8695X-EVAL | 功能描述:网络开发工具 KSZ8695X Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| KSZ8721B | 功能描述:以太网 IC 10/100 BASE-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8721B TR | 功能描述:以太网 IC 10/100 BASE-TX/FX Physical Layer Transceiver, Single 3.3V Supply, 48-SSOP (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8721B | 制造商:Micrel Inc 功能描述:Transceiver IC 制造商:Micrel Inc 功能描述:IC, TRANSCEIVER, SSOP-48 |
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