参数资料
型号: KSZ8851-16MLLI
厂商: Micrel Inc
文件页数: 33/84页
文件大小: 0K
描述: IC MAC CTLR 1PORT W/BUS 48-TQFP
标准包装: 250
控制器类型: 以太网控制器,MAC/PHY
接口: 总线
电源电压: 1.8V,2.5V,3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
其它名称: 576-3505
Micrel, Inc.
KSZ8851-16MLL/MLLI
March 11, 2014
39
Revision 2.2
Register Map: MAC, PHY and QMU
Do not write to bit values or to registers defined as Reserved. ManIPUlating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
WO = Write only.
RW = Read/Write.
W1C = Write 1 to Clear (writing an “1” to clear this bit).
0x00 – 0x07: Reserved
Chip Configuration Register (0x08 – 0x09): CCR
This register indicates the chip configuration mode based on strapping and bonding options
Bit
Default Value
R/W
Description
15-11
-
RO
Reserved.
10
-
RO
Bus Endian mode
The EESK (pin 10) value is latched into this bit druing power-up/reset.
0: Bus in Big Endian mode, 1: Bus in Little Endian mode.
9
-
RO
EEPROM presence
The EED_IO (pin 9) value is latched into this bit druing power-up/reset.
0: No external EEPROM, 1: Use external EEPROM.
8
0
RO
Reserved.
7
-
RO
8-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 8-bit bus mode operation, 1: In 8-bit bus mode operation.
6
-
RO
16-Bit data bus width
This bit value is loaded from P1LED1 (pin 1)
0: Not in 16-bit bus mode operation, 1: In 16-bit bus mode operation.
5
0
RO
Reserved.
4
-
RO
Shared data bus mode for data and address
0: Data and address bus are seperated.
1: Data and address bus are shared.
3
0
RO
Reserved.
2
0
RO
Reserved.
1
-
RO
48-Pin Chip Package
To indicate chip package is 48-pin.
0: No, 1: Yes.
0
RO
Reserved.
0x0A – 0x0F: Reserved
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