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参数资料
| 型号： | KSZ8862-16MQL-FX |
| 厂商： | Micrel Inc |
| 文件页数： | 55/125页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH ETH 2P 16BIT 128PQFP |
| 标准包装： | 66 |
| 系列： | KSZ8862 |
| 控制器类型： | 以太网开关控制器 |
| 接口： | PCI |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-BFQFP |
| 供应商设备封装： | 128-PQFP（14x20） |
| 包装： | 托盘 |
| 产品目录页面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1638-ND - BOARD EVALUATION KSZ8862-10FL 576-1637-ND - BOARD EVALUATION KSZ8862-100FX |
| 其它名称： | 576-3271 |
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Micrel, Inc.
KSZ8862-16/32MQL
April 2007
35
M9999-040407-3.0
Signal
Type
(1)
Function
RDYRTNN
I
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.
For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that the
wait states are inserted by system logic (memory) not by KSZ8862M.
BCLK
I
Bus Clock
Asynchronous Transfer Signals
RDN
I
Asynchronous Read
WRN
I
Asynchronous Write
ARDY
O
Asynchronous Ready
This signal is asserted (low) to insert wait states.
Table 2. Bus Interface Unit Signal Grouping
Legend:
I = Input.
O = Output.
I/O = Bi-directional.
Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge of
ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Note: Whether the transfer is synchronous or asynchronous, if the local device decoder is used, LDEVN will be asserted
to indicate that the KSZ8862M is successfully targeted. Basically, signal LDEVN is a combinatorial decode of AEN and
A[15:4].
Asynchronous Interface
For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the
synchronous dedicated signals BCLK, CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level
throughout the entire asynchronous transfer.
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three
major ways of interfacing with the system (host) are.
1.
Interfacing with the system/host relying on local device decoding and having stable address throughout the whole
transfer:
The typical example for this application is ISA-like bus interface using latched address signals as shown in the Figure
16. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes A[15:4] and
qualifies with AEN (Address Enable) to determine if the KSZ8862M switch is the intended target. The host utilizes the
rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.
2.
Interfacing with the system/host relying on local device decoding but not having stable address throughout the entire
transfer: the typical example for this application is EISA-like bus (non-burst) interface as shown in the Figure 17. This
type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4] and
qualifies with AEN to determine if the KSZ8862M switch is the intended target. The data transfer is the same as the
first case.
3.
Interfacing with the system/host relying on central decoding (KSZ8862-32 mode only).
The typical example for this application is for an embedded processor having a central decoder on the system board
or within the processor. Connecting the chip select (CS) from system/host to DATACSN bypasses the local device
decoder. When the DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N,
BE1N, and BE0N are ignored as shown in the Figure 18. No other registers can be accessed by asserting DATACSN.
The data transfer is the same as in the first case, independent of the type of asynchronous interface used. To insert a
wait state, the BIU will assert ARDY to prolong the cycle.
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