参数资料
型号: KSZ8862-16MQL-FX
厂商: Micrel Inc
文件页数: 83/125页
文件大小: 0K
描述: IC SWITCH ETH 2P 16BIT 128PQFP
标准包装: 66
系列: KSZ8862
控制器类型: 以太网开关控制器
接口: PCI
安装类型: 表面贴装
封装/外壳: 128-BFQFP
供应商设备封装: 128-PQFP(14x20)
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名称: 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
60
M9999-040407-3.0
Bank 3 EEPROM Control Register (0x02): EEPCR
To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external
EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an
EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are loaded
from the EEPROM immediately after reset. The KSZ8862M allows the software to access (read and write) the EEPROM
directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software Access bit is
set.
Bit
Default Value
R/W
Description
15-5
-
RO
Reserved
4
0
RW
EESA EEPROM Software Access
1: enable software to access EEPROM through bit 3 to bit 0.
0: disable software to access EEPROM.
3
-
RO
EECB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EEDI pin.
2-0
0x0
RW
EECB EEPROM Control Bits
Bit 2: Data Transmit to EEPROM. This bit directly controls the device’s EEDO pin.
Bit 1: Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0: Chip Select for EEPROM. This bit directly controls the device’s EECS pin.
Bank 3 Memory BIST INFO Register (0x04): MBIR
Bit
Default Value
R/W
Description
15-13
0x0
RO
Reserved
12
-
RO
TXMBF TX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the TX Memory.
11
-
RO
TXMBFA TX Memory Bist Fail
When set, it indicates the Memory Built In Self Test has failed.
10-5
-
RO
Reserved
4
-
RO
RXMBF RX Memory Bist Finish
When set, it indicates the Memory Built In Self Test completion for the RX Memory.
3
-
RO
RXMBFA RX Memory Bist Fail
When set, it indicates the Memory Built In Self Test has failed.
2-0
-
RO
Reserved
Bank 3 Global Reset Register (0x06): GRR
This register controls the global reset function with information programmed by the CPU.
Bit
Default Value
R/W
Description
15-1
0x0000
RO
Reserved
0
RW
Global Soft Reset
1: software reset is active.
0: software reset is inactive.
Software reset will affect PHY, MAC, QMU, DMA, and the switch core, only the BIU (base
address registers) remains unaffected by a software reset.
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