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| 型号： | KSZ8863RLLI |
| 厂商： | Micrel Inc |
| 文件页数： | 55/106页 |
| 文件大小： | 0K |
| 描述： | IC ETHERNET SWITCH 3PORT 48-LQFP |
| 标准包装： | 250 |
| 控制器类型： | 以太网开关控制器 |
| 接口： | MII |
| 电源电压： | 1.8V，2.5V，3.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 配用： | 576-3868-ND - BOARD EVALUATION FOR KSZ8863RLL |
| 其它名称： | 576-3752 |
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PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 51
8.4.2
MASTER OPERATION
Master operation is supported in rmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a reset or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I2C bus may be taken when the P bit is set, or the
bus is idle and both the S and P bits are clear.
In master operation, the SCL and SDA lines are manip-
ulated in rmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
transmitting data, a '1' data bit must have the
TRISC<4> bit set (input) and a '0' data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Data transfer byte transmitted/received
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see
AN554
- Software Implementation of I2C Bus Master.
8.4.3
MULTI-MASTER OPERATION
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
Address Transfer
Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
For more information on master operation, see
AN578
- Use of the SSP Module in the of I2C Multi-Master
Environment.
TABLE 8-4
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
(1)
ADIF
(1)
SSPIF
CCP1IF TMR2IF TMR1IF
0000 0000
8Ch
PIE1
(1)
ADIE
(1)
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD Synchronous Serial Port (I2C mode) Address Register
0000 0000
14h
SSPCON
WCOL
SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
0000 0000
94h
SSPSTAT
SMP(2)
CKE(2)
D/A
P
S
R/W
UA
BF
0000 0000
87h
TRISC
PORTC Data Direction register
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1:
These bits are unimplemented, read as '0'.
2:
The SMP and CKE bits are implemented on the PIC16CR72 only. On the PIC16C72, these two bits are unimplemented,
read as '0'.
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