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参数资料
| 型号： | L99PD08 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 17/41页 |
| 文件大小： | 750K |
| 代理商： | L99PD08 |
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SPI
L99PD08
24/41
Doc ID 15872 Rev 3
Figure 9.
SPI frame structure
6.2.1
Serial clock (SCK)
This input signal provides the timing of the serial interface. Data present at Serial Data Input
(SDI) is latched on the rising edge of Serial Clock (SCK). Data on Serial Data Out (SDO) is
shifted out at the falling edge of Serial Clock (SCK).
The writing to the selected data input register is only enabled if exactly one frame length is
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame the complete frame will be ignored and a SPI frame error is
signaled in the Global Status register. This safety function is implemented to avoid an
unwanted activation of output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
CSN
SDO
SDI
Command Byte
(8 bit)
Global Status Byte
(8 bit)
Data
(8 bit)
MSB
LSB
Data
(previous content of register )
Write Operation
CSN
SDO
SDI
Command Byte
(8 bit)
Global Status Byte
(8 bit)
All 0
(8 bit)
MSB
LSB
Data
(8 bit)
Read Operation
MSB
LSB
MSB
LSB
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