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参数资料
| 型号： | L99PD08 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 19/41页 |
| 文件大小： | 750K |
| 代理商： | L99PD08 |
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SPI
L99PD08
26/41
Doc ID 15872 Rev 3
6.3.3
Operating code definition
The <Write Mode> and <Read Mode> operations allow access to the RAM of the device,
e.g. write to control registers or read status information.
A <Clear Status> Operation addressed to a device specific status register will read back and
subsequently clear this status register. A <Clear Status> Operation with address 3FH clears
all status registers at a time and reads back the <Configuration> byte.
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version and register width.
6.3.4
Global status byte
Table 20.
Operating code definition
OC1
OC0
Description
0
<Write Mode>
0
1
<Read Mode>
1
0
<Clear Status>
1
<Read Device Information>
Table 21.
Global status byte
Bit
7
6
5
4
3
2
1
0
Name
Global error
flag
Communication
error
No (chip reset or
communication
error)
Over temp/
over load
n/a
Open-
load
STK_ON
Fail save
Table 22.
Global status byte: description
Name
Polarity
Comment
Global error flag
Active high
Logical OR combination of all failures in the
<Global Status Register> (initially set to '1').
Communication error
Active high
Set if the number of clock cycles during CSN low
does not match with the specified frame width.
SDI stuck at '0' will force the LHOME-bit to be
cleared and is not signaled as a communication
error. SDI stuck at '1' will lead to a software reset
and is therefore not signaled as a
communication error. FAIL SAVE is entered in
both cases.
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