- 您现在的位置：买卖IC网 > PDF目录19773 > LA4128ZC-75TN100E (Lattice Semiconductor Corporation)IC CPLD 128MACROCELLS 100TQFP PDF资料下载
参数资料
| 型号： | LA4128ZC-75TN100E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 2/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MACROCELLS 100TQFP |
| 标准包装： | 90 |
| 系列： | LA-ispMACH |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 1.7 V ~ 1.9 V |
| 宏单元数： | 128 |
| 输入/输出数： | 64 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
第1页当前第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
10
Figure 8. I/O Cell
Each output supports a variety of output standards dependent on the VCCO supplied to its I/O bank. Outputs can
also be congured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the VCCO supplied to its I/O bank. The I/O standards supported are:
LVTTL
LVCMOS 1.8
LVCMOS 3.3
3.3V PCI Compatible
LVCMOS 2.5
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
congured to be a Pull-up Resistor.
Each LA-ispMACH 4000V/Z automotive device I/O has an individually programmable output slew rate control bit.
Each output can be individually congured for fast slew or slow slew. The typical edge rate difference between fast
and slow slew setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will intro-
duce fewer reections, less noise and keep ground bounce to a minimum. For designs with short traces or well ter-
minated lines, the fast slew rate can be used to achieve the highest speed.
Global OE Generation
Most LA-ispMACH 4000V/Z automotive family devices have a 4-bit wide Global OE Bus, except the LA-ispMACH
4032V and LA-ispMACH4032Z devices that have a 2-bit wide Global OE Bus. This bus is derived from a 4-bit inter-
nal global OE PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be
inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
128-macrocell device (with 16 blocks), each line of the bus is driven from 8 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
GOE 0
From ORP
*Global fuses
From ORP
To Macrocell
To GRP
GOE 1
GOE 2
GOE 3
VCC
VCCO
**
*
相关PDF资料 |
PDF描述 |
|---|---|
| ISPLSI 2096A-100LQN128 | IC PLD ISP 96I/O 10NS 128PQFP |
| ASC08DTES | CONN EDGECARD 16POS .100 EYELET |
| TAP106M016SRS | CAP TANT 10UF 16V 20% RADIAL |
| VE-25D-EV-F3 | CONVERTER MOD DC/DC 85V 150W |
| VE-B5P-CY-F4 | CONVERTER MOD DC/DC 13.8V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LA4128ZC-75TN128E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN144E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN44E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN48E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZV-75TN100E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
发布紧急采购，3分钟左右您将得到回复。