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参数资料
| 型号： | LA4128ZC-75TN100E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 39/42页 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MACROCELLS 100TQFP |
| 标准包装： | 90 |
| 系列： | LA-ispMACH |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 1.7 V ~ 1.9 V |
| 宏单元数： | 128 |
| 输入/输出数： | 64 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
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Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
6
Table 5. Product Term Expansion Capability
Every time the super cluster allocator is used, there is an incremental delay of tEXP. When the super cluster alloca-
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Enhanced Clock Multiplexer
The clock input to the ip-op can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
Block CLK0
Block CLK1
Block CLK2
Expansion Chains
Macrocells Associated with Expansion Chain (with Wrap Around)
Max PT/Macrocell
Chain-0
M0
→ M4 → M8 → M12 → M0
75
Chain-1
M1
→ M5 → M9 → M13 → M1
80
Chain-2
M2
→ M6 → M10 → M14 → M2
75
Chain-3
M3
→ M7 → M11 → M15 → M3
70
Single PT
Block CLK0
Block CLK1
Block CLK2
Block CLK3
PT Clock (optional)
Shared PT Clock
CE
D/T/L
Q
RP
Shared PT Initialization
PT Initialization/CE (optional)
PT Initialization (optional)
From Logic Allocator
Power-up
Initialization
To ORP
To GRP
From I/O Cell
Delay
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LA4128ZC-75TN128E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN144E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN44E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZC-75TN48E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LA4128ZV-75TN100E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs |
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