参数资料
型号: LA4128ZC-75TN100E
厂商: Lattice Semiconductor Corporation
文件页数: 7/42页
文件大小: 0K
描述: IC CPLD 128MACROCELLS 100TQFP
标准包装: 90
系列: LA-ispMACH
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 7.5ns
电压电源 - 内部: 1.7 V ~ 1.9 V
宏单元数: 128
输入/输出数: 64
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
15
I/O Recommended Operating Conditions
DC Electrical Characteristics
Over Recommended Operating Conditions
Standard
VCCO (V)
1
Min.
Max.
LVTTL
3.0
3.6
LVCMOS 3.3
3.0
3.6
Extended LVCMOS 3.3
2
2.7
3.6
LVCMOS 2.5
2.3
2.7
LVCMOS 1.8
1.65
1.95
PCI 3.3
3.0
3.6
1. Typical values for VCCO are the average of the min. and max. values.
2. LA-ispMACH 4000Z only.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
IIL, IIH
1, 4
Input Leakage Current
(LA-ispMACH 4000Z)
0 ≤ VIN < VCCO
0.5
1
A
IIH
1, 2
Input High Leakage Current
(LA-ispMACH 4000V)
3.6V < VIN ≤ 5.5V, Tj = 105°C
3.0V ≤ VCCO ≤ 3.6V
20
A
3.6V < VIN ≤ 5.5V, Tj = 130°C
3.0V ≤ VCCO ≤ 3.6V
50
A
Input High Leakage Current
(LA-ispMACH 4000Z)
VCCO < VIN ≤ 5.5V
10
A
IPU
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000V)
0 ≤ VIN ≤ 0.7VCCO
-30
-200
A
I/O Weak Pull-up Resistor Current
(LA-ispMACH 4000Z)
0 ≤ VIN ≤ 0.7VCCO
-30
-150
A
IPD
I/O Weak Pull-down Resistor Current VIL (MAX) ≤ VIN ≤ VIH (MIN)
30
150
A
IBHLS
Bus Hold Low Sustaining Current
VIN = VIL (MAX)
30
A
IBHHS
Bus Hold High Sustaining Current
VIN = 0.7 VCCO
-30
A
IBHLO
Bus Hold Low Overdrive Current
0V ≤ VIN ≤ VBHT
150
A
IBHHO
Bus Hold High Overdrive Current
VBHT ≤ VIN ≤ VCCO
-150
A
VBHT
Bus Hold Trip Points
VCCO * 0.35
VCCO * 0.65
V
C1
I/O Capacitance
3
VCCO = 3.3V, 2.5V, 1.8V
8
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
C2
Clock Capacitance
3
VCCO = 3.3V, 2.5V, 1.8V
6
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
C3
Global Input Capacitance
3
VCCO = 3.3V, 2.5V, 1.8V
6
pf
VCC = 1.8V, VIO = 0 to VIH (MAX)
1. Input or I/O leakage current is measured with the pin congured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ VCCO ≤ 3.6V.
3. TA = 25°C, f = 1.0MHz.
4. IIH excursions of up to 1.5A maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
the device’s I/O pins.
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