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| 型号： | LAMXO256C-3TN100E |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 34/77页 |
| 文件大小： | 0K |
| 描述： | IC FPGA AUTO 256LUTS 100-TQFP |
| 标准包装： | 90 |
| 系列： | LA-MachXO |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.9ns |
| 电压电源 - 内部： | 1.71 V ~ 3.465 V |
| 宏单元数： | 128 |
| 输入/输出数： | 78 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | 220-1637 LAMXO256C-3TN100E-ND |
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February 2007
Data Sheet DS1003
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
2-1
DS1003 Architecture_01.2
Architecture Overview
The LA-MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO).
Some devices in this family have sysCLOCK PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Fig-
The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a
column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks.
The PIOs utilize a exible I/O buffer referred to as a sysIO interface that supports operation with a variety of inter-
face standards. The blocks are connected with many vertical and horizontal routing channel resources. The place
and route software tool automatically allocates these routing resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register func-
tions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and
PFF blocks are optimized for exibility, allowing complex designs to be implemented quickly and effectively. Logic
blocks are arranged in a two-dimensional array. Only one type of block is used per row.
In the LA-MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on
different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast
memory blocks; these blocks are found only in the larger devices. These blocks can be congured as RAM, ROM
or FIFO. FIFO support includes dedicated FIFO pointer and ag “hard” control logic to minimize LUT use.
The LA-MachXO architecture provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on larger devices.
These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting
capabilities that are used to manage the frequency and phase relationships of the clocks.
Every device in the family has a JTAG Port that supports programming and conguration of the device as well as
access to the user logic. The LA-MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power
supplies, providing easy integration into the overall system.
LA-MachXO Automotive Family Data Sheet
Architecture
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相关代理商/技术参数 |
参数描述 |
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| LAMXO256E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
| LAMXO256E-3TN100E | 功能描述:CPLD - 复杂可编程逻辑器件 Auto Grade (AEC-Q100 ) MachXO256E RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LAMXO256LUTSC-3FTN256E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
| LAMXO256LUTSC-3FTN324E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
| LAMXO256LUTSC-3TN100E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:LA-MachXO Automotive Family Data Sheet |
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