参数资料
型号: LAMXO256C-3TN100E
厂商: Lattice Semiconductor Corporation
文件页数: 77/77页
文件大小: 0K
描述: IC FPGA AUTO 256LUTS 100-TQFP
标准包装: 90
系列: LA-MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 4.9ns
电压电源 - 内部: 1.71 V ~ 3.465 V
宏单元数: 128
输入/输出数: 78
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
其它名称: 220-1637
LAMXO256C-3TN100E-ND
2-6
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Figure 2-6. Distributed Memory Primitives
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during conguration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Routing
There are many resources provided in the LA-MachXO devices to route signals individually or as buses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efcient connec-
tions in the horizontal and vertical directions.
Logic
Ripple
RAM
ROM
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
LUT 6x 2 or
MUX 8x1 x 2
2-bit Counter x 4
SPR16x8 x 1
ROM16x4 x 2
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
ROM16x8 x 1
DO1
DO0
DI0
DI1
AD0
AD1
AD2
AD3
WRE
CK
DO0
AD0
AD1
AD2
AD3
DPR16x2
SPR16x2
ROM16x1
RDO1
RDO0
DI0
DI1
WCK
WRE
WDO1
WDO0
WAD0
WAD1
WAD2
WAD3
RAD0
RAD1
RAD2
RAD3
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