参数资料
型号: LAMXO640E-3FTN256E
厂商: Lattice Semiconductor Corporation
文件页数: 2/77页
文件大小: 0K
描述: IC FPGA 640LUTS 256TQFP
标准包装: 90
系列: LA-MachXO
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 4.9ns
电压电源 - 内部: 1.14 V ~ 1.26 V
宏单元数: 320
输入/输出数: 159
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-FTBGA(17x17)
包装: 托盘
2-7
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network
The LA-MachXO automotive family of devices provides global signals that are available to all PFUs. These signals
consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes
as shown in Figure 2-7 and Figure 2-8. The available clock sources for the LA-MachXO256 and LA-MachXO640
devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the LA-
MachXO1200 and LA-MachXO2280 devices are four dual function clock pins, up to nine internal routing signals
and up to six PLL outputs.
Figure 2-7. Primary Clocks for LA-MachXO256 and LA-MachXO640 Devices
Routing
Clock
Pads
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
4
12
16:1
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