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参数资料
| 型号： | LC5256B-10T128I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 12 ns, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 23/66页 |
| 文件大小： | 240K |
| 代理商： | LC5256B-10T128I |
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Lattice Semiconductor
ispMACH 5000B Family Data Sheet
3
and complement form for every product term. The three control product terms are used for shared reset, clock and
output enable functions.
AND-Array
The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs from the GRP are
used to form 136 lines in the AND-array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 163 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-
OR Array with the remaining three control product terms feeding the Shared PT Clock, Shared PT Reset, and
Shared PT OE. Every set of ve product terms from the 160 logic product terms forms a product term cluster start-
ing with PT0. There is one product term cluster for every macrocell in the GLB. In addition to the three control prod-
uct terms, the rst, third, fourth and fth product terms of each cluster can be used as a PTOE (output macrocells
only), PT Clock, PT Preset and PT Reset, respectively. Figure 2 is a graphical representation of the AND-Array.
Figure 2. ispMACH 5000B AND-Array
Dual-OR Array
There are two OR gates per macrocell in the GLB. These OR gates are referred to as the PTSA OR gate and the
PTSA-Bypass OR gate. The PTSA-Bypass OR gate receives its ve inputs from the combination of product terms
associated with the product term cluster. The PTSA-Bypass OR gate feeds the macrocell directly for fast narrow
logic. The PTSA OR gate receives its inputs from the combination of product terms associated with the product
term cluster. Figure 3 shows the Dual-OR Array.
PT0
PT1
Cluster 0
PT2
PT3
PT4
In[0]
In[66]
In[67]
Note:
Indicates programmable fuse.
PT160
PT161
PT162
Shared clock
Shared reset
Shared OE
PT156
PT157
PT158
PT159
PT155
Cluster 31
Discontinued
Product
(PCN
#02-06).
Contact
Rochester
Electronics
for
Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
相关PDF资料 |
PDF描述 |
|---|---|
| LC5256B-75Q208I | |
| LC5256B-5Q208C | |
| LC5384B-4F256C | |
| LC5256B-4Q208C | |
| LC5384B-5Q208C | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC5256B-4F256C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5256B-4Q208C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5256B-4T128C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5256B-5F256C | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| LC5256B-5F256I | 功能描述:CPLD - 复杂可编程逻辑器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
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