参数资料
型号: LC5256B-10T128I
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
中文描述: EE PLD, 12 ns, PQFP128
封装: TQFP-128
文件页数: 7/66页
文件大小: 240K
代理商: LC5256B-10T128I
Lattice Semiconductor
ispMACH 5000B Family Data Sheet
15
ispMACH 5256B External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
-4
-5
-75
-10
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tPD
Data propagation delay, 5-PT bypass
-
4.0
-
5.0
-
7.5
-
10.0
ns
tPD_PTSA
Propagation delay
-
4.8
-
6.5
-
9.0
-
12.0
ns
tS
GLB register setup time before clock, 5-PT
bypass
2.1
-
3.0
-
5.0
-
6.5
-
ns
tS_PTSA
GLB register setup time before clock
2.7
-
4.0
-
6.5
-
8.5
-
ns
tSIR
GLB register setup time before clock, input reg-
ister path, 5-PT bypass
1.9
-
2.5
-
3.5
-
5.0
-
ns
tH
GLB register hold time before clock, 5-PT
bypass
0.0
-
0.0
-
0.0
-
0.0
-
ns
tH_PTSA
GLB register hold time before clock
0.0
-
0.0
-
0.0
-
0.0
-
ns
tHIR
GLB register hold time before clock, input
reg.path
0.0
-
0.0
-
0.0
-
0.0
-
ns
tCO
GLB register clock-to-output delay
-
2.7
-
3.0
-
4.0
-
5.5
ns
tR
External reset pin to output delay
-
3.8
-
5.0
-
7.5
-
10.0
ns
tRW
Reset pulse duration
3.0
-
3.5
5.0
-
6.5
-
ns
tPTEN/DIS
Input to output local product term output
enable/disable
-
5.0
-
6.0
-
8.5
-
10.0
ns
tGPTEN/DIS Input to output global product term output
enable/disable
-
5.5
-
7.0
-
10.0
-
12.0
ns
tGOE/DIS
Global OE input to output enable/disable
-
3.4
-
3.7
-
5.5
-
7.5
ns
tCW
Clock pulse duration
1.5
-
2.2
-
2.5
-
2.8
-
ns
tGW
Global gate width low (for low transparent) or
high (for high transparent)
1.5
-
2.2
-
2.5
-
2.8
-
ns
tWIR
Input register clock width, high or low
1.5
-
2.2
-
2.5
-
2.8
-
ns
fMAX
4
Clock frequency with internal feedback
250
-
180
-
150
-
110
-
MHz
fMAX (Ext.) Clock frequency with external feedback,
1/(tS_PTSA + tCO)
185
-
142
-
95
-
71
-
MHz
fMAX (Tog.) Clock frequency max toggle
333
-
225
-
200
-
175
-
MHz
Timing v.1.3
1. Timing Numbers are based on default LVCMOS 2.5V, 8mA I/O buffers. Use timing adjusters provided to calculate timing for other stan-
dards.
2. Measured using standard switching circuit, assuming global routing loading of 1, worst case PTSA loading, CLK0, 1 output switching and
high speed AND array.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
Discontinued
Product
(PCN
#02-06).
Contact
Rochester
Electronics
for
Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
相关PDF资料
PDF描述
LC5256B-75Q208I
LC5256B-5Q208C
LC5384B-4F256C
LC5256B-4Q208C
LC5384B-5Q208C
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