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| 型号： | LC5512MC-75Q208I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 9.5 ns, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 23/95页 |
| 文件大小： | 923K |
| 代理商： | LC5512MC-75Q208I |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
3
5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing
Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance
access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs
are provided to allow the synthesis of new clocks and control of clock skews.
Multi-Function Block (MFB)
Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides
a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that
are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are:
SuperWIDE Logic Mode
True Dual-port SRAM Mode
Pseudo Dual-port SRAM Mode
Single-port SRAM Mode
FIFO Mode
Ternary CAM Mode
The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multi-
function array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs
data along with certain control functions to the macrocells. Output signals can be routed internally for use else-
where in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various
configurations are described in more detail in the following sections.
Figure 2. MFB Block Diagram
To Routing
Reset
CLK0
CLK3
CLK1
CLK2
PTOE
Sharing
To
I/O
via
OSA
Cascade
In
Cascade Out
Multifunction Array
True Dual Port
RAM
(8,192 bit)
Pseudo Dual
Port RAM
(16,384 bit)
Single Port
RAM
(16,384 bit)
FIFO
(16,384 bit)
Ternary CAM
(128*48)
Logic
(68 Input * 164 Product
Term Array, 32 MC)
32
Feedback
Signals
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相关代理商/技术参数 |
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| LC5512MC-75Q256C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q484C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q484I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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