- 您现在的位置：买卖IC网 > PDF目录177666 > LC5512MC-75Q208I (LATTICE SEMICONDUCTOR CORP) PDF资料下载
参数资料
| 型号： | LC5512MC-75Q208I |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 中文描述： | EE PLD, 9.5 ns, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 5/95页 |
| 文件大小： | 923K |
| 代理商： | LC5512MC-75Q208I |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
13
FIFO Mode
In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The
read and write clocks can be different or the same dependent on the application. Four flags show the status of the
FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro-
grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica-
tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read
address.
In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 12 shows the block diagram of the FIFO.
Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share
the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead
mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared
by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg-
isters.
Figure 12. FIFO Block Diagram
Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode
Register
Input
Source
Write Data,
Write Enable
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
N/A
Full and
Almost Full
Flags
Clock
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
Read Data,
Empty and
Almost Empty
Flags
Clock
RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
Clock
Enable
RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
‘
68 Inputs
From
Routing
Write Clock (WCLK)
Write Enable (WE)
Reset (RST)
Read Enable (RE)
Read Clock (RCLK)
Reset_RP (RSTRP)
Write Data
(DI[0:0-31])
16,384-bit
SRAM
Array
FIFO
Control
Logic
*Control logic can be
duplicated in adjacent MFB
in 32-bit mode
RESET
CLK0
CLK3
CLK1
CLK2
Read Data
(DO[0:0-31])
FIFO
Flags*
Full, Empty,
Almost Full,
AlmostEmpty
相关PDF资料 |
PDF描述 |
|---|---|
| LC5512MC-75F256I | |
| LC5256MC-5F256I | |
| LC5512MB-45F484C | |
| LC5256MC-75F256I | |
| LC51024MC-52F672C | |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LC5512MC-75Q256C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q256I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q484C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q484I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q672C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
发布紧急采购，3分钟左右您将得到回复。